mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0fd57f4b56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207510 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
4.1 KiB
C++
122 lines
4.1 KiB
C++
//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the AArch64TargetMachine
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// methods. Principally just setting up the passes needed to generate correct
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// code on this architecture.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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extern "C" void LLVMInitializeAArch64Target() {
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RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
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RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
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}
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AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool LittleEndian)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, LittleEndian),
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InstrInfo(Subtarget),
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DL(LittleEndian ?
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"e-m:e-i64:64-i128:128-n32:64-S128" :
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"E-m:e-i64:64-i128:128-n32:64-S128"),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget) {
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initAsmInfo();
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}
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void AArch64leTargetMachine::anchor() { }
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AArch64leTargetMachine::
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AArch64leTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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void AArch64beTargetMachine::anchor() { }
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AArch64beTargetMachine::
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AArch64beTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our AArch64 pass. This
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// allows the AArch64 pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createAArch64TargetTransformInfoPass(this));
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}
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namespace {
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/// AArch64 Code Generator Pass Configuration Options.
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class AArch64PassConfig : public TargetPassConfig {
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public:
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AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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AArch64TargetMachine &getAArch64TargetMachine() const {
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return getTM<AArch64TargetMachine>();
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}
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const AArch64Subtarget &getAArch64Subtarget() const {
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return *getAArch64TargetMachine().getSubtargetImpl();
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}
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addPreEmitPass() override;
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};
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} // namespace
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bool AArch64PassConfig::addPreISel() {
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createGlobalMergePass(TM));
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return false;
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}
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TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AArch64PassConfig(this, PM);
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}
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bool AArch64PassConfig::addPreEmitPass() {
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addPass(&UnpackMachineBundlesID);
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addPass(createAArch64BranchFixupPass());
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return true;
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}
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bool AArch64PassConfig::addInstSelector() {
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addPass(createAArch64ISelDAG(getAArch64TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses.
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if (getAArch64Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
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addPass(createAArch64CleanupLocalDynamicTLSPass());
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return false;
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}
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