Justin Holewinski 0ff4287fe2 [NVPTX] Add support for selecting CUDA vs OCL mode based on triple ... IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-21 18:51:49 +00:00
..
AArch64	AArch64: remove accidental test output file.	2013-06-18 21:16:53 +00:00
ARM	ARM: Remove a (false) dependency on the memoryoperand's value as we do not use	2013-06-20 22:51:44 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	[mips] Add an IR transformation pass that optimizes calls to sqrt.	2013-06-11 22:21:44 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Add support for selecting CUDA vs OCL mode based on triple	2013-06-21 18:51:49 +00:00
PowerPC	[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.	2013-06-13 20:23:34 +00:00
R600	R600/SI: Expand sub for v2i32 and v4i32 for SI	2013-06-20 21:55:37 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	Add missing REQUIRES: asserts in crash.ll.	2013-06-21 18:47:08 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00