Tom Stellard 0ffcaa0d54 SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type ... The legalizer can now do this type of expansion for more type combinations without loading and storing to and from the stack. NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195398 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-22 00:41:05 +00:00
..
AArch64	Implemented Neon scalar vdup_lane intrinsics.	2013-11-21 08:16:15 +00:00
ARM	[ARM] add the overlooked tests for Cortex-A7 build attributes	2013-11-21 16:22:39 +00:00
CPP	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Generic	Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."	2013-11-21 10:55:15 +00:00
Hexagon	TBAA: remove !tbaa from testing cases when they are not needed.	2013-09-30 18:17:35 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.	2013-11-21 16:11:31 +00:00
MSP430	Make sure SP is always aligned on a 2 byte boundary	2013-10-24 09:32:31 +00:00
NVPTX	[NVPTX] Fix handling of indirect calls	2013-11-15 12:30:04 +00:00
PowerPC	PPC popcnt[dw] do not have record forms	2013-11-20 20:54:55 +00:00
R600	SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type	2013-11-22 00:41:05 +00:00
SPARC	[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.	2013-11-03 12:28:40 +00:00
SystemZ	[SystemZ] Automatically detect zEC12 and z196 hosts	2013-10-31 12:14:17 +00:00
Thumb	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
Thumb2	Enable generating legacy IT block for AArch32	2013-11-13 18:29:49 +00:00
X86	SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.	2013-11-21 23:21:26 +00:00
XCore	Error if we see an alias to a declaration.	2013-11-14 13:58:06 +00:00