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d950941e13
Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
281 lines
9.3 KiB
C++
281 lines
9.3 KiB
C++
//===- BlackfinInstrInfo.cpp - Blackfin Instruction Information -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Blackfin implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "BlackfinInstrInfo.h"
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#include "BlackfinSubtarget.h"
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#include "Blackfin.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "BlackfinGenInstrInfo.inc"
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using namespace llvm;
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BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
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: TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts)),
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RI(ST, *this),
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Subtarget(ST) {}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg,
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unsigned &DstReg,
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unsigned &SrcSR,
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unsigned &DstSR) const {
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SrcSR = DstSR = 0; // No sub-registers.
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switch (MI.getOpcode()) {
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case BF::MOVE:
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case BF::MOVE_ncccc:
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case BF::MOVE_ccncc:
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case BF::MOVECC_zext:
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case BF::MOVECC_nz:
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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case BF::SLL16i:
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if (MI.getOperand(2).getImm()!=0)
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return false;
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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default:
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return false;
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}
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned BlackfinInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case BF::LOAD32fi:
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case BF::LOAD16fi:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned BlackfinInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case BF::STORE32fi:
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case BF::STORE16fi:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned BlackfinInstrInfo::
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InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc operand
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DebugLoc dl = DebugLoc::getUnknownLoc();
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"Branch conditions have one component!");
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, dl, get(BF::JUMPa)).addMBB(TBB);
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return 1;
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}
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// Conditional branch.
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llvm_unreachable("Implement conditional branches!");
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}
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static bool inClass(const TargetRegisterClass &Test,
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unsigned Reg,
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const TargetRegisterClass *RC) {
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return Test.contains(Reg);
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else
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return &Test==RC || Test.hasSubClass(RC);
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}
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bool BlackfinInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc dl = DebugLoc::getUnknownLoc();
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if (inClass(BF::ALLRegClass, DestReg, DestRC) &&
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inClass(BF::ALLRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVE), DestReg).addReg(SrcReg);
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return true;
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}
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if (inClass(BF::D16RegClass, DestReg, DestRC) &&
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inClass(BF::D16RegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0);
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return true;
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}
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if (inClass(BF::AnyCCRegClass, SrcReg, SrcRC) &&
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inClass(BF::DRegClass, DestReg, DestRC)) {
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if (inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVENCC_z), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, dl, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
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} else {
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BuildMI(MBB, I, dl, get(BF::MOVECC_zext), DestReg).addReg(SrcReg);
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}
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return true;
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}
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if (inClass(BF::AnyCCRegClass, DestReg, DestRC) &&
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inClass(BF::DRegClass, SrcReg, SrcRC)) {
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if (inClass(BF::NotCCRegClass, DestReg, DestRC))
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BuildMI(MBB, I, dl, get(BF::SETEQri_not), DestReg).addReg(SrcReg);
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else
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BuildMI(MBB, I, dl, get(BF::MOVECC_nz), DestReg).addReg(SrcReg);
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return true;
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}
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if (inClass(BF::NotCCRegClass, DestReg, DestRC) &&
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inClass(BF::JustCCRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg);
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return true;
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}
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if (inClass(BF::JustCCRegClass, DestReg, DestRC) &&
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inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg);
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return true;
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}
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llvm_unreachable((std::string("Bad regclasses for reg-to-reg copy: ")+
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SrcRC->getName() + " -> " + DestRC->getName()).c_str());
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return false;
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}
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void
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BlackfinInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg,
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bool isKill,
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int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = I != MBB.end() ?
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I->getDebugLoc() : DebugLoc::getUnknownLoc();
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if (inClass(BF::DPRegClass, SrcReg, RC)) {
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BuildMI(MBB, I, DL, get(BF::STORE32fi))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0);
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return;
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}
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if (inClass(BF::D16RegClass, SrcReg, RC)) {
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BuildMI(MBB, I, DL, get(BF::STORE16fi))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0);
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return;
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}
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if (inClass(BF::AnyCCRegClass, SrcReg, RC)) {
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BuildMI(MBB, I, DL, get(BF::STORE8fi))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0);
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return;
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}
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llvm_unreachable((std::string("Cannot store regclass to stack slot: ")+
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RC->getName()).c_str());
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}
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void BlackfinInstrInfo::
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storeRegToAddr(MachineFunction &MF,
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unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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llvm_unreachable("storeRegToAddr not implemented");
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}
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void
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BlackfinInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = I != MBB.end() ?
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I->getDebugLoc() : DebugLoc::getUnknownLoc();
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if (inClass(BF::DPRegClass, DestReg, RC)) {
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BuildMI(MBB, I, DL, get(BF::LOAD32fi), DestReg)
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.addFrameIndex(FI)
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.addImm(0);
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return;
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}
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if (inClass(BF::D16RegClass, DestReg, RC)) {
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BuildMI(MBB, I, DL, get(BF::LOAD16fi), DestReg)
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.addFrameIndex(FI)
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.addImm(0);
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return;
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}
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if (inClass(BF::AnyCCRegClass, DestReg, RC)) {
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BuildMI(MBB, I, DL, get(BF::LOAD8fi), DestReg)
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.addFrameIndex(FI)
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.addImm(0);
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return;
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}
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llvm_unreachable("Cannot load regclass from stack slot");
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}
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void BlackfinInstrInfo::
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loadRegFromAddr(MachineFunction &MF,
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unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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llvm_unreachable("loadRegFromAddr not implemented");
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}
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