mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-29 11:29:39 +00:00
108934c65d
X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
409 lines
11 KiB
LLVM
409 lines
11 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
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declare void @bar(i32)
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declare void @car(i32)
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declare void @dar(i32)
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declare void @ear(i32)
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declare void @far(i32)
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declare i1 @qux()
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@GHJK = global i32 0
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@HABC = global i32 0
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; BranchFolding should tail-merge the stores since they all precede
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; direct branches to the same place.
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; CHECK: tail_merge_me:
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; CHECK-NOT: GHJK
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: movl $1, HABC(%rip)
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; CHECK-NOT: GHJK
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define void @tail_merge_me() nounwind {
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entry:
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%a = call i1 @qux()
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br i1 %a, label %A, label %next
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next:
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%b = call i1 @qux()
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br i1 %b, label %B, label %C
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A:
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call void @bar(i32 0)
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store i32 0, i32* @GHJK
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br label %M
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B:
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call void @car(i32 1)
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store i32 0, i32* @GHJK
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br label %M
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C:
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call void @dar(i32 2)
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store i32 0, i32* @GHJK
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br label %M
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M:
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store i32 1, i32* @HABC
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%c = call i1 @qux()
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br i1 %c, label %return, label %altret
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return:
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call void @ear(i32 1000)
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ret void
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altret:
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call void @far(i32 1001)
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ret void
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}
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declare i8* @choose(i8*, i8*);
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; BranchFolding should tail-duplicate the indirect jump to avoid
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; redundant branching.
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; CHECK: tail_duplicate_me:
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%rbx
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%rbx
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%rbx
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define void @tail_duplicate_me() nounwind {
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entry:
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%a = call i1 @qux()
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%c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
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i8* blockaddress(@tail_duplicate_me, %altret))
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br i1 %a, label %A, label %next
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next:
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%b = call i1 @qux()
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br i1 %b, label %B, label %C
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A:
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call void @bar(i32 0)
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store i32 0, i32* @GHJK
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br label %M
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B:
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call void @car(i32 1)
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store i32 0, i32* @GHJK
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br label %M
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C:
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call void @dar(i32 2)
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store i32 0, i32* @GHJK
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br label %M
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M:
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indirectbr i8* %c, [label %return, label %altret]
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return:
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call void @ear(i32 1000)
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ret void
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altret:
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call void @far(i32 1001)
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ret void
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}
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; BranchFolding shouldn't try to merge the tails of two blocks
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; with only a branch in common, regardless of the fallthrough situation.
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; CHECK: dont_merge_oddly:
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; CHECK-NOT: ret
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; CHECK: ucomiss %xmm0, %xmm1
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; CHECK-NEXT: jbe .LBB3_3
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; CHECK-NEXT: ucomiss %xmm2, %xmm0
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; CHECK-NEXT: ja .LBB3_4
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_3:
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; CHECK-NEXT: ucomiss %xmm2, %xmm1
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; CHECK-NEXT: jbe .LBB3_2
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; CHECK-NEXT: .LBB3_4:
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; CHECK-NEXT: xorb %al, %al
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; CHECK-NEXT: ret
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define i1 @dont_merge_oddly(float* %result) nounwind {
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entry:
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%tmp4 = getelementptr float* %result, i32 2
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%tmp5 = load float* %tmp4, align 4
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%tmp7 = getelementptr float* %result, i32 4
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%tmp8 = load float* %tmp7, align 4
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%tmp10 = getelementptr float* %result, i32 6
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%tmp11 = load float* %tmp10, align 4
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%tmp12 = fcmp olt float %tmp8, %tmp11
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br i1 %tmp12, label %bb, label %bb21
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bb:
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%tmp23469 = fcmp olt float %tmp5, %tmp8
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br i1 %tmp23469, label %bb26, label %bb30
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bb21:
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%tmp23 = fcmp olt float %tmp5, %tmp11
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br i1 %tmp23, label %bb26, label %bb30
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bb26:
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ret i1 0
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bb30:
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ret i1 1
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}
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; Do any-size tail-merging when two candidate blocks will both require
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; an unconditional jump to complete a two-way conditional branch.
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; CHECK: c_expand_expr_stmt:
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; CHECK: jmp .LBB4_7
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; CHECK-NEXT: .LBB4_12:
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; CHECK-NEXT: movq 8(%rax), %rax
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; CHECK-NEXT: movb 16(%rax), %al
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; CHECK-NEXT: cmpb $16, %al
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; CHECK-NEXT: je .LBB4_6
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; CHECK-NEXT: cmpb $23, %al
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; CHECK-NEXT: je .LBB4_6
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; CHECK-NEXT: jmp .LBB4_15
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; CHECK-NEXT: .LBB4_14:
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; CHECK-NEXT: cmpb $23, %bl
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; CHECK-NEXT: jne .LBB4_15
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; CHECK-NEXT: .LBB4_15:
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%0 = type { %struct.rtx_def* }
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%struct.lang_decl = type opaque
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%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] }
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%struct.tree_decl = type { [24 x i8], i8*, i32, %union.tree_node*, i32, i8, i8, i8, i8, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %union..2anon, %0, %union.tree_node*, %struct.lang_decl* }
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%union..2anon = type { i32 }
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%union.rtunion = type { i8* }
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%union.tree_node = type { %struct.tree_decl }
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define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind {
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entry:
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%tmp4 = load i8* null, align 8 ; <i8> [#uses=3]
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switch i8 %tmp4, label %bb3 [
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i8 18, label %bb
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]
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bb: ; preds = %entry
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switch i32 undef, label %bb1 [
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i32 0, label %bb2.i
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i32 37, label %bb.i
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]
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bb.i: ; preds = %bb
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switch i32 undef, label %bb1 [
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i32 0, label %lvalue_p.exit
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]
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bb2.i: ; preds = %bb
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br label %bb3
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lvalue_p.exit: ; preds = %bb.i
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%tmp21 = load %union.tree_node** null, align 8 ; <%union.tree_node*> [#uses=3]
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%tmp22 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1]
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%tmp23 = load i8* %tmp22, align 8 ; <i8> [#uses=1]
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%tmp24 = zext i8 %tmp23 to i32 ; <i32> [#uses=1]
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switch i32 %tmp24, label %lvalue_p.exit4 [
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i32 0, label %bb2.i3
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i32 2, label %bb.i1
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]
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bb.i1: ; preds = %lvalue_p.exit
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%tmp25 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1]
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%tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
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%tmp27 = load %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2]
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%tmp28 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
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%tmp29 = load i8* %tmp28, align 8 ; <i8> [#uses=1]
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%tmp30 = zext i8 %tmp29 to i32 ; <i32> [#uses=1]
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switch i32 %tmp30, label %lvalue_p.exit4 [
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i32 0, label %bb2.i.i2
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i32 2, label %bb.i.i
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]
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bb.i.i: ; preds = %bb.i1
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%tmp34 = tail call fastcc i32 @lvalue_p(%union.tree_node* null) nounwind ; <i32> [#uses=1]
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%phitmp = icmp ne i32 %tmp34, 0 ; <i1> [#uses=1]
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br label %lvalue_p.exit4
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bb2.i.i2: ; preds = %bb.i1
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%tmp35 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
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%tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
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%tmp37 = load %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1]
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%tmp38 = getelementptr inbounds %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
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%tmp39 = load i8* %tmp38, align 8 ; <i8> [#uses=1]
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switch i8 %tmp39, label %bb2 [
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i8 16, label %lvalue_p.exit4
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i8 23, label %lvalue_p.exit4
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]
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bb2.i3: ; preds = %lvalue_p.exit
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%tmp40 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
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%tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
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%tmp42 = load %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1]
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%tmp43 = getelementptr inbounds %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
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%tmp44 = load i8* %tmp43, align 8 ; <i8> [#uses=1]
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switch i8 %tmp44, label %bb2 [
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i8 16, label %lvalue_p.exit4
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i8 23, label %lvalue_p.exit4
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]
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lvalue_p.exit4: ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit
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%tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1]
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%tmp46 = icmp eq i8 %tmp4, 0 ; <i1> [#uses=1]
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%or.cond = or i1 %tmp45, %tmp46 ; <i1> [#uses=1]
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br i1 %or.cond, label %bb2, label %bb3
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bb1: ; preds = %bb2.i.i, %bb.i, %bb
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%.old = icmp eq i8 %tmp4, 23 ; <i1> [#uses=1]
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br i1 %.old, label %bb2, label %bb3
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bb2: ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2
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br label %bb3
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bb3: ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry
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%expr_addr.0 = phi %union.tree_node* [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <%union.tree_node*> [#uses=0]
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unreachable
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}
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declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly
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declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
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; If one tail merging candidate falls through into the other,
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; tail merging is likely profitable regardless of how few
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; instructions are involved. This function should have only
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; one ret instruction.
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; CHECK: foo:
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; CHECK: callq func
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: ret
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define void @foo(i1* %V) nounwind {
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entry:
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%t0 = icmp eq i1* %V, null
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br i1 %t0, label %return, label %bb
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bb:
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call void @func()
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ret void
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return:
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ret void
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}
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declare void @func()
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; one - One instruction may be tail-duplicated even with optsize.
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; CHECK: one:
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; CHECK: movl $0, XYZ(%rip)
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; CHECK: movl $0, XYZ(%rip)
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@XYZ = external global i32
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define void @one() nounwind optsize {
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entry:
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%0 = icmp eq i32 undef, 0
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br i1 %0, label %bbx, label %bby
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bby:
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switch i32 undef, label %bb7 [
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i32 16, label %return
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]
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bb7:
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volatile store i32 0, i32* @XYZ
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unreachable
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bbx:
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switch i32 undef, label %bb12 [
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i32 128, label %return
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]
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bb12:
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volatile store i32 0, i32* @XYZ
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unreachable
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return:
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ret void
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}
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; two - Same as one, but with two instructions in the common
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; tail instead of one. This is too much to be merged, given
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; the optsize attribute.
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; CHECK: two:
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; CHECK-NOT: XYZ
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; CHECK: movl $0, XYZ(%rip)
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; CHECK: movl $1, XYZ(%rip)
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; CHECK-NOT: XYZ
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; CHECK: ret
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define void @two() nounwind optsize {
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entry:
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%0 = icmp eq i32 undef, 0
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br i1 %0, label %bbx, label %bby
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bby:
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switch i32 undef, label %bb7 [
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i32 16, label %return
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]
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bb7:
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volatile store i32 0, i32* @XYZ
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volatile store i32 1, i32* @XYZ
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unreachable
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bbx:
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switch i32 undef, label %bb12 [
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i32 128, label %return
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]
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bb12:
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volatile store i32 0, i32* @XYZ
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volatile store i32 1, i32* @XYZ
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unreachable
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return:
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ret void
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}
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; two_nosize - Same as two, but without the optsize attribute.
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; Now two instructions are enough to be tail-duplicated.
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; CHECK: two_nosize:
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; CHECK: movl $0, XYZ(%rip)
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; CHECK: movl $1, XYZ(%rip)
|
|
; CHECK: movl $0, XYZ(%rip)
|
|
; CHECK: movl $1, XYZ(%rip)
|
|
|
|
define void @two_nosize() nounwind {
|
|
entry:
|
|
%0 = icmp eq i32 undef, 0
|
|
br i1 %0, label %bbx, label %bby
|
|
|
|
bby:
|
|
switch i32 undef, label %bb7 [
|
|
i32 16, label %return
|
|
]
|
|
|
|
bb7:
|
|
volatile store i32 0, i32* @XYZ
|
|
volatile store i32 1, i32* @XYZ
|
|
unreachable
|
|
|
|
bbx:
|
|
switch i32 undef, label %bb12 [
|
|
i32 128, label %return
|
|
]
|
|
|
|
bb12:
|
|
volatile store i32 0, i32* @XYZ
|
|
volatile store i32 1, i32* @XYZ
|
|
unreachable
|
|
|
|
return:
|
|
ret void
|
|
}
|