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https://github.com/c64scene-ar/llvm-6502.git
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8ce6c58e41
r213101 changed the behaviour of this method to not only affect the PostMachineScheduler scheduler but also the PostRAScheduler scheduler, renaming should make this fact clear. Also document that the preferred way is to specify this in the scheduling model instead of overriding this method. Differential Revision: http://reviews.llvm.org/D10427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239659 91177308-0d34-0410-b5e6-96231b3b80d8
362 lines
12 KiB
C++
362 lines
12 KiB
C++
//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMSubtarget.h"
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#include "ARMFrameLowering.h"
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#include "ARMISelLowering.h"
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#include "ARMInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSelectionDAGInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "Thumb1FrameLowering.h"
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#include "Thumb1InstrInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "arm-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "ARMGenSubtargetInfo.inc"
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static cl::opt<bool>
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ReserveR9("arm-reserve-r9", cl::Hidden,
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cl::desc("Reserve R9, making it unavailable as GPR"));
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static cl::opt<bool>
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ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
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static cl::opt<bool>
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UseFusedMulOps("arm-use-mulops",
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cl::init(true), cl::Hidden);
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namespace {
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enum AlignMode {
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DefaultAlign,
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StrictAlign,
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NoStrictAlign
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};
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}
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static cl::opt<AlignMode>
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Align(cl::desc("Load/store alignment support"),
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cl::Hidden, cl::init(DefaultAlign),
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cl::values(
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clEnumValN(DefaultAlign, "arm-default-align",
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"Generate unaligned accesses only on hardware/OS "
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"combinations that are known to support them"),
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clEnumValN(StrictAlign, "arm-strict-align",
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"Disallow all unaligned memory accesses"),
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clEnumValN(NoStrictAlign, "arm-no-strict-align",
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"Allow unaligned memory accesses"),
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clEnumValEnd));
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enum ITMode {
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DefaultIT,
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RestrictedIT,
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NoRestrictedIT
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};
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static cl::opt<ITMode>
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IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
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cl::ZeroOrMore,
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cl::values(clEnumValN(DefaultIT, "arm-default-it",
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"Generate IT block based on arch"),
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clEnumValN(RestrictedIT, "arm-restrict-it",
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"Disallow deprecated IT based on ARMv8"),
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clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
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"Allow IT blocks based on ARMv7"),
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clEnumValEnd));
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/// initializeSubtargetDependencies - Initializes using a CPU and feature string
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/// so that we can use initializer lists for subtarget initialization.
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ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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initializeEnvironment();
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initSubtargetFeatures(CPU, FS);
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return *this;
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}
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ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
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StringRef FS) {
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ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
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if (STI.isThumb1Only())
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return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
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return new ARMFrameLowering(STI);
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}
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ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const ARMBaseTargetMachine &TM, bool IsLittle)
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: ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
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ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
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TargetTriple(TT), Options(TM.Options), TM(TM),
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TSInfo(*TM.getDataLayout()),
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FrameLowering(initializeFrameLowering(CPU, FS)),
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// At this point initializeSubtargetDependencies has been called so
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// we can query directly.
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InstrInfo(isThumb1Only()
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? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
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: !isThumb()
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? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
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: (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
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TLInfo(TM, *this) {}
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void ARMSubtarget::initializeEnvironment() {
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HasV4TOps = false;
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HasV5TOps = false;
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HasV5TEOps = false;
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HasV6Ops = false;
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HasV6MOps = false;
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HasV6KOps = false;
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HasV6T2Ops = false;
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HasV7Ops = false;
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HasV8Ops = false;
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HasV8_1aOps = false;
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HasVFPv2 = false;
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HasVFPv3 = false;
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HasVFPv4 = false;
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HasFPARMv8 = false;
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HasNEON = false;
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UseNEONForSinglePrecisionFP = false;
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UseMulOps = UseFusedMulOps;
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SlowFPVMLx = false;
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HasVMLxForwarding = false;
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SlowFPBrcc = false;
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InThumbMode = false;
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UseSoftFloat = false;
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HasThumb2 = false;
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NoARM = false;
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IsR9Reserved = ReserveR9;
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UseMovt = false;
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SupportsTailCall = false;
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HasFP16 = false;
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HasD16 = false;
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HasHardwareDivide = false;
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HasHardwareDivideInARM = false;
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HasT2ExtractPack = false;
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HasDataBarrier = false;
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Pref32BitThumb = false;
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AvoidCPSRPartialUpdate = false;
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AvoidMOVsShifterOperand = false;
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HasRAS = false;
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HasMPExtension = false;
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HasVirtualization = false;
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FPOnlySP = false;
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HasPerfMon = false;
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HasTrustZone = false;
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HasCrypto = false;
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HasCRC = false;
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HasZeroCycleZeroing = false;
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AllowsUnalignedMem = false;
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Thumb2DSP = false;
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UseNaClTrap = false;
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UnsafeFPMath = false;
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}
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void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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if (CPUString.empty()) {
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if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
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// Default to the Swift CPU when targeting armv7s/thumbv7s.
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CPUString = "swift";
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else
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CPUString = "generic";
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}
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// Insert the architecture feature derived from the target triple into the
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// feature string. This is important for setting features that are implied
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// based on the architecture version.
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std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = (Twine(ArchFS) + "," + FS).str();
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else
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ArchFS = FS;
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}
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ParseSubtargetFeatures(CPUString, ArchFS);
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// FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
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// Assert this for now to make the change obvious.
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assert(hasV6T2Ops() || !hasThumb2());
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// Keep a pointer to static instruction cost data for the specified CPU.
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SchedModel = getSchedModelForCPU(CPUString);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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// FIXME: this is invalid for WindowsCE
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if (isTargetWindows())
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NoARM = true;
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if (isAAPCS_ABI())
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stackAlignment = 8;
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if (isTargetNaCl())
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stackAlignment = 16;
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UseMovt = hasV6T2Ops() && ArmUseMOVT;
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if (isTargetMachO()) {
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IsR9Reserved = ReserveR9 || !HasV6Ops;
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SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
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} else {
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IsR9Reserved = ReserveR9;
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SupportsTailCall = !isThumb1Only();
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}
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if (Align == DefaultAlign) {
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// Assume pre-ARMv6 doesn't support unaligned accesses.
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//
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// ARMv6 may or may not support unaligned accesses depending on the
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// SCTLR.U bit, which is architecture-specific. We assume ARMv6
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// Darwin and NetBSD targets support unaligned accesses, and others don't.
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//
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// ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
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// which raises an alignment fault on unaligned accesses. Linux
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// defaults this bit to 0 and handles it as a system-wide (not
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// per-process) setting. It is therefore safe to assume that ARMv7+
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// Linux targets support unaligned accesses. The same goes for NaCl.
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//
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// The above behavior is consistent with GCC.
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AllowsUnalignedMem =
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(hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
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isTargetNetBSD())) ||
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(hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
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} else {
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AllowsUnalignedMem = !(Align == StrictAlign);
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}
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// No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
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if (isV6M())
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AllowsUnalignedMem = false;
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switch (IT) {
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case DefaultIT:
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RestrictIT = hasV8Ops();
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break;
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case RestrictedIT:
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RestrictIT = true;
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break;
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case NoRestrictedIT:
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RestrictIT = false;
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break;
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}
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// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
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const FeatureBitset &Bits = getFeatureBits();
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if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
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(Options.UnsafeFPMath || isTargetDarwin()))
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UseNEONForSinglePrecisionFP = true;
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}
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bool ARMSubtarget::isAPCS_ABI() const {
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assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
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return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
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}
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bool ARMSubtarget::isAAPCS_ABI() const {
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assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
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return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS;
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}
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/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
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bool
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ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
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Reloc::Model RelocM) const {
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if (RelocM == Reloc::Static)
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return false;
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bool isDecl = GV->isDeclarationForLinker();
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if (!isTargetMachO()) {
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return false;
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return true;
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} else {
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if (RelocM == Reloc::PIC_) {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage())
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// Hidden $non_lazy_ptr reference.
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return true;
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return false;
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} else {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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}
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}
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return false;
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}
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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return SchedModel.MispredictPenalty;
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}
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bool ARMSubtarget::hasSinCos() const {
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return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
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}
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// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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bool ARMSubtarget::enablePostRAScheduler() const {
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return (!isThumb() || hasThumb2());
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}
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bool ARMSubtarget::enableAtomicExpand() const {
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return hasAnyDataBarrier() && !isThumb1Only();
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}
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bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
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// NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
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// immediates as it is inherently position independent, and may be out of
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// range otherwise.
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return UseMovt && (isTargetWindows() ||
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!MF.getFunction()->hasFnAttribute(Attribute::MinSize));
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}
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bool ARMSubtarget::useFastISel() const {
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// Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
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return TM.Options.EnableFastISel &&
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((isTargetMachO() && !isThumb1Only()) ||
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(isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
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}
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