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simultaneously. Move that pass to SimpleRegisterCoalescing. This makes it easier to implement alternative register allocation and coalescing strategies while maintaining reuse of the existing live interval analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37520 91177308-0d34-0410-b5e6-96231b3b80d8
161 lines
5.8 KiB
C++
161 lines
5.8 KiB
C++
//===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a simple register copy coalescing phase.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
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#define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/IndexedMap.h"
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namespace llvm {
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class LiveVariables;
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class MRegisterInfo;
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class TargetInstrInfo;
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class VirtRegMap;
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class SimpleRegisterCoalescing : public MachineFunctionPass {
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const MRegisterInfo* mri_;
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const TargetInstrInfo* tii_;
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LiveIntervals *li_;
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LiveVariables *lv_;
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typedef IndexedMap<unsigned> Reg2RegMap;
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Reg2RegMap r2rMap_;
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BitVector allocatableRegs_;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
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/// JoinedLIs - Keep track which register intervals have been coalesced
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/// with other intervals.
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BitVector JoinedLIs;
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public:
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static char ID; // Pass identifcation, replacement for typeid
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SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {};
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struct CopyRec {
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MachineInstr *MI;
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unsigned SrcReg, DstReg;
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};
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CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
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CopyRec R;
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R.MI = MI;
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R.SrcReg = SrcReg;
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R.DstReg = DstReg;
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return R;
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}
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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};
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(std::ostream &O, const Module* = 0) const;
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void print(std::ostream *O, const Module* M = 0) const {
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if (O) print(*O, M);
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}
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private:
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/// joinIntervals - join compatible live intervals
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void joinIntervals();
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/// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
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/// copies that cannot yet be coallesced into the "TryAgain" list.
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void CopyCoallesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> *TryAgain, bool PhysOnly = false);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coallesced away, or if it is never possible
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/// to coallesce these this copy, due to register constraints. It returns
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/// false if it is not currently possible to coallesce this interval, but
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/// it may be possible if other things get coallesced.
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bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
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bool PhysOnly = false);
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/// JoinIntervals - Attempt to join these two intervals. On failure, this
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/// returns false. Otherwise, if one of the intervals being joined is a
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/// physreg, this method always canonicalizes DestInt to be it. The output
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/// "SrcInt" will not have been modified, so we can use this information
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/// below to update aliases.
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bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS);
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/// SimpleJoin - Attempt to join the specified interval into this one. The
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/// caller of this method must guarantee that the RHS only contains a single
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/// value number and that the RHS is not defined by a copy from this
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/// interval. This returns false if the intervals are not joinable, or it
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/// joins them and returns true.
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bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
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/// Return true if the two specified registers belong to different
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/// register classes. The registers may be either phys or virt regs.
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bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
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bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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MachineInstr *CopyMI);
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/// lastRegisterUse - Returns the last use of the specific register between
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/// cycles Start and End. It also returns the use operand by reference. It
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/// returns NULL if there are no uses.
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MachineInstr *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
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MachineOperand *&MOU);
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/// findDefOperand - Returns the MachineOperand that is a def of the specific
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/// register. It returns NULL if the def is not found.
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MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
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/// unsetRegisterKill - Unset IsKill property of all uses of the specific
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/// register of the specific instruction.
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void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
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/// unsetRegisterKills - Unset IsKill property of all uses of specific register
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/// between cycles Start and End.
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void unsetRegisterKills(unsigned Start, unsigned End, unsigned Reg);
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/// hasRegisterDef - True if the instruction defines the specific register.
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///
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bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
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/// rep - returns the representative of this register
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unsigned rep(unsigned Reg) {
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unsigned Rep = r2rMap_[Reg];
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if (Rep)
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return r2rMap_[Reg] = rep(Rep);
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return Reg;
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}
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void printRegName(unsigned reg) const;
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};
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} // End llvm namespace
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#endif
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