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https://github.com/c64scene-ar/llvm-6502.git
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5bafff36c7
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.5 KiB
LLVM
86 lines
2.5 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vceq\\.i8} %t | count 2
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; RUN: grep {vceq\\.i16} %t | count 2
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; RUN: grep {vceq\\.i32} %t | count 2
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; RUN: grep vmvn %t | count 6
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; RUN: grep {vcgt\\.s8} %t | count 1
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; RUN: grep {vcge\\.s16} %t | count 1
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; RUN: grep {vcgt\\.u16} %t | count 1
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; RUN: grep {vcge\\.u32} %t | count 1
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; This tests vicmp operations that do not map directly to NEON instructions.
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; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)
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; and less-than-or-equal (le/ule) are implemented by swapping the arguments
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; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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; the other operations.
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define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = vicmp ne <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = vicmp ne <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = vicmp ne <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = vicmp ne <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = vicmp ne <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = vicmp ne <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = vicmp slt <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = vicmp sle <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = vicmp ult <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = vicmp ule <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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