mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
37e671e894
Added new types to Legalizer. Fixed getSetCCResultType function Added lowering tests. Reviewed by Elena Demikhovsky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216717 91177308-0d34-0410-b5e6-96231b3b80d8
313 lines
9.6 KiB
LLVM
313 lines
9.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vcmpleps
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; CHECK: vmovaps
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
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%mask = fcmp ole <16 x float> %x, %y
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%max = select <16 x i1> %mask, <16 x float> %x, <16 x float> %y
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ret <16 x float> %max
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}
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; CHECK-LABEL: test2
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; CHECK: vcmplepd
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; CHECK: vmovapd
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; CHECK: ret
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define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
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%mask = fcmp ole <8 x double> %x, %y
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%max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %y
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ret <8 x double> %max
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}
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; CHECK-LABEL: test3
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; CHECK: vpcmpeqd (%rdi)
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %yp) nounwind {
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%y = load <16 x i32>* %yp, align 4
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%mask = icmp eq <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test4_unsigned
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; CHECK: vpcmpnltud
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y) nounwind {
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%mask = icmp uge <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
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ret <16 x i32> %max
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}
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; CHECK-LABEL: test5
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; CHECK: vpcmpeqq {{.*}}%k1
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
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%mask = icmp eq <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test6_unsigned
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; CHECK: vpcmpnleuq {{.*}}%k1
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <8 x i64> @test6_unsigned(<8 x i64> %x, <8 x i64> %y) nounwind {
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%mask = icmp ugt <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test7
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; CHECK: xor
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; CHECK: vcmpltps
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; CHECK: vblendvps
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; CHECK: ret
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define <4 x float> @test7(<4 x float> %a, <4 x float> %b) {
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%mask = fcmp olt <4 x float> %a, zeroinitializer
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%c = select <4 x i1>%mask, <4 x float>%a, <4 x float>%b
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ret <4 x float>%c
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}
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; CHECK-LABEL: test8
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; CHECK: xor
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; CHECK: vcmpltpd
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; CHECK: vblendvpd
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; CHECK: ret
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define <2 x double> @test8(<2 x double> %a, <2 x double> %b) {
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%mask = fcmp olt <2 x double> %a, zeroinitializer
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%c = select <2 x i1>%mask, <2 x double>%a, <2 x double>%b
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ret <2 x double>%c
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}
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; CHECK-LABEL: test9
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; CHECK: vpcmpeqd
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; CHECK: vpblendmd
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; CHECK: ret
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define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind {
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%mask = icmp eq <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test10
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; CHECK: vcmpeqps
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; CHECK: vblendmps
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; CHECK: ret
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define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind {
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%mask = fcmp oeq <8 x float> %x, %y
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%max = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
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ret <8 x float> %max
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}
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; CHECK-LABEL: test11_unsigned
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; CHECK: vpmaxud
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; CHECK: ret
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define <8 x i32> @test11_unsigned(<8 x i32> %x, <8 x i32> %y) nounwind {
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%mask = icmp ugt <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test12
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; CHECK: vpcmpeqq %zmm2, %zmm0, [[LO:%k[0-7]]]
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; CHECK: vpcmpeqq %zmm3, %zmm1, [[HI:%k[0-7]]]
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; CHECK: kunpckbw [[LO]], [[HI]], {{%k[0-7]}}
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define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind {
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%res = icmp eq <16 x i64> %a, %b
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%res1 = bitcast <16 x i1> %res to i16
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ret i16 %res1
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}
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; CHECK-LABEL: test13
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; CHECK: vcmpeqps %zmm
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; CHECK: vpbroadcastd
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; CHECK: ret
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define <16 x i32> @test13(<16 x float>%a, <16 x float>%b)
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{
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%cmpvector_i = fcmp oeq <16 x float> %a, %b
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%conv = zext <16 x i1> %cmpvector_i to <16 x i32>
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ret <16 x i32> %conv
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}
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; CHECK-LABEL: test14
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; CHECK: vpcmp
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; CHECK-NOT: vpcmp
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; CHECK: vmovdqu32 {{.*}}{%k1} {z}
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; CHECK: ret
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define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
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%sub_r = sub <16 x i32> %a, %b
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%cmp.i2.i = icmp sgt <16 x i32> %sub_r, %a
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%sext.i3.i = sext <16 x i1> %cmp.i2.i to <16 x i32>
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%mask = icmp eq <16 x i32> %sext.i3.i, zeroinitializer
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%res = select <16 x i1> %mask, <16 x i32> zeroinitializer, <16 x i32> %sub_r
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test15
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; CHECK: vpcmpgtq
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; CHECK-NOT: vpcmp
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; CHECK: vmovdqu64 {{.*}}{%k1} {z}
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; CHECK: ret
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define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
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%sub_r = sub <8 x i64> %a, %b
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%cmp.i2.i = icmp sgt <8 x i64> %sub_r, %a
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%sext.i3.i = sext <8 x i1> %cmp.i2.i to <8 x i64>
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%mask = icmp eq <8 x i64> %sext.i3.i, zeroinitializer
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%res = select <8 x i1> %mask, <8 x i64> zeroinitializer, <8 x i64> %sub_r
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ret <8 x i64>%res
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}
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; CHECK-LABEL: @test16
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; CHECK: vpcmpled
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test16(<16 x i32> %x, <16 x i32> %y) nounwind {
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%mask = icmp sge <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test17
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; CHECK: vpcmpgtd (%rdi)
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test17(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
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%y = load <16 x i32>* %y.ptr, align 4
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%mask = icmp sgt <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test18
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; CHECK: vpcmpled (%rdi)
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test18(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
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%y = load <16 x i32>* %y.ptr, align 4
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%mask = icmp sle <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test19
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; CHECK: vpcmpleud (%rdi)
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test19(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
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%y = load <16 x i32>* %y.ptr, align 4
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%mask = icmp ule <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test20
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; CHECK: vpcmpeqd %zmm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test20(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i32> %y1) nounwind {
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%mask1 = icmp eq <16 x i32> %x1, %y1
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%mask0 = icmp eq <16 x i32> %x, %y
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%mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test21
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; CHECK: vpcmpleq %zmm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <8 x i64> @test21(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y1) nounwind {
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%mask1 = icmp sge <8 x i64> %x1, %y1
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%mask0 = icmp sle <8 x i64> %x, %y
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%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
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ret <8 x i64> %max
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}
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; CHECK-LABEL: @test22
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; CHECK: vpcmpgtq (%rdi){{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <8 x i64> @test22(<8 x i64> %x, <8 x i64>* %y.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
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%mask1 = icmp sgt <8 x i64> %x1, %y1
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%y = load <8 x i64>* %y.ptr, align 4
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%mask0 = icmp sgt <8 x i64> %x, %y
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%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
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ret <8 x i64> %max
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}
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; CHECK-LABEL: @test23
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; CHECK: vpcmpleud (%rdi){{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test23(<16 x i32> %x, <16 x i32>* %y.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
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%mask1 = icmp sge <16 x i32> %x1, %y1
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%y = load <16 x i32>* %y.ptr, align 4
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%mask0 = icmp ule <16 x i32> %x, %y
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%mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: test24
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; CHECK: vpcmpeqq (%rdi){1to8}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
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%yb = load i64* %yb.ptr, align 4
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%y.0 = insertelement <8 x i64> undef, i64 %yb, i32 0
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%y = shufflevector <8 x i64> %y.0, <8 x i64> undef, <8 x i32> zeroinitializer
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%mask = icmp eq <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test25
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; CHECK: vpcmpled (%rdi){1to16}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind {
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%yb = load i32* %yb.ptr, align 4
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%y.0 = insertelement <16 x i32> undef, i32 %yb, i32 0
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%y = shufflevector <16 x i32> %y.0, <16 x i32> undef, <16 x i32> zeroinitializer
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%mask = icmp sle <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: test26
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; CHECK: vpcmpgtd (%rdi){1to16}{{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
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%mask1 = icmp sge <16 x i32> %x1, %y1
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%yb = load i32* %yb.ptr, align 4
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%y.0 = insertelement <16 x i32> undef, i32 %yb, i32 0
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%y = shufflevector <16 x i32> %y.0, <16 x i32> undef, <16 x i32> zeroinitializer
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%mask0 = icmp sgt <16 x i32> %x, %y
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%mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: test27
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; CHECK: vpcmpleq (%rdi){1to8}{{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <8 x i64> @test27(<8 x i64> %x, i64* %yb.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
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%mask1 = icmp sge <8 x i64> %x1, %y1
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%yb = load i64* %yb.ptr, align 4
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%y.0 = insertelement <8 x i64> undef, i64 %yb, i32 0
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%y = shufflevector <8 x i64> %y.0, <8 x i64> undef, <8 x i32> zeroinitializer
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%mask0 = icmp sle <8 x i64> %x, %y
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%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
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ret <8 x i64> %max
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}
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