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6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.3 KiB
LLVM
37 lines
1.3 KiB
LLVM
; Without list-burr scheduling we may not see the difference in codegen here.
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; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
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; breaker requires liveness information to be kept.
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; RUN: llc < %s -march=x86-64 -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=list-burr -break-anti-dependencies=none > %t
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; RUN: grep "%xmm0" %t | count 14
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; RUN: not grep "%xmm1" %t
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; RUN: llc < %s -march=x86-64 -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical > %t
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; RUN: grep "%xmm0" %t | count 7
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; RUN: grep "%xmm1" %t | count 7
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define void @goo(double* %r, double* %p, double* %q) nounwind {
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entry:
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%0 = load double* %p, align 8
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%1 = fadd double %0, 1.100000e+00
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%2 = fmul double %1, 1.200000e+00
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%3 = fadd double %2, 1.300000e+00
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%4 = fmul double %3, 1.400000e+00
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%5 = fadd double %4, 1.500000e+00
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%6 = fptosi double %5 to i32
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%7 = load double* %r, align 8
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%8 = fadd double %7, 7.100000e+00
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%9 = fmul double %8, 7.200000e+00
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%10 = fadd double %9, 7.300000e+00
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%11 = fmul double %10, 7.400000e+00
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%12 = fadd double %11, 7.500000e+00
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%13 = fptosi double %12 to i32
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%14 = icmp slt i32 %6, %13
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br i1 %14, label %bb, label %return
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bb:
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store double 9.300000e+00, double* %q, align 8
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ret void
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return:
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ret void
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}
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