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d24d326705
which have successfully round-tripped through the combine phase, and use this to ensure all operands to DAG nodes are visited by the combiner, even if they are only added during the combine phase. This is critical to have the combiner reach nodes that are *introduced* during combining. Previously these would sometimes be visited and sometimes not be visited based on whether they happened to end up on the worklist or not. Now we always run them through the combiner. This fixes quite a few bad codegen test cases lurking in the suite while also being more principled. Among these, the TLS codegeneration is particularly exciting for programs that have this in the critical path like TSan-instrumented binaries (although I think they engineer to use a different TLS that is faster anyways). I've tried to check for compile-time regressions here by running llc over a merged (but not LTO-ed) clang bitcode file and observed at most a 3% slowdown in llc. Given that this is essentially a worst case (none of opt or clang are running at this phase) I think this is tolerable. The actual LTO case should be even less costly, and the cost in normal compilation should be negligible. With this combining logic, it is possible to re-legalize as we combine which is necessary to implement PSHUFB formation on x86 as a post-legalize DAG combine (my ultimate goal). Differential Revision: http://reviews.llvm.org/D4638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213898 91177308-0d34-0410-b5e6-96231b3b80d8
231 lines
8.6 KiB
LLVM
231 lines
8.6 KiB
LLVM
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.2 | FileCheck %s
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; Test based on pr5626 to load/store
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;
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%i32vec3 = type <3 x i32>
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define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
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; CHECK-LABEL: add3i32:
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; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: paddd (%{{.*}}), %[[R0]]
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; CHECK-NEXT: pextrd $2, %[[R0]], 8(%{{.*}})
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; CHECK-NEXT: movq %[[R0]], (%{{.*}})
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%a = load %i32vec3* %ap, align 16
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%b = load %i32vec3* %bp, align 16
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%x = add %i32vec3 %a, %b
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store %i32vec3 %x, %i32vec3* %ret, align 16
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ret void
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}
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define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
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; CHECK-LABEL: add3i32_2:
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; CHECK: movq (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: pinsrd $2, 8(%{{.*}}), %[[R0]]
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; CHECK-NEXT: movq (%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: pinsrd $2, 8(%{{.*}}), %[[R1]]
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; CHECK-NEXT: paddd %[[R0]], %[[R1]]
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; CHECK-NEXT: pextrd $2, %[[R1]], 8(%{{.*}})
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; CHECK-NEXT: movq %[[R1]], (%{{.*}})
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%a = load %i32vec3* %ap, align 8
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%b = load %i32vec3* %bp, align 8
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%x = add %i32vec3 %a, %b
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store %i32vec3 %x, %i32vec3* %ret, align 8
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ret void
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}
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%i32vec7 = type <7 x i32>
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define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) {
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; CHECK-LABEL: add7i32:
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; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: paddd (%{{.*}}), %[[R0]]
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; CHECK-NEXT: paddd 16(%{{.*}}), %[[R1]]
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; CHECK-NEXT: pextrd $2, %[[R1]], 24(%{{.*}})
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; CHECK-NEXT: movq %[[R1]], 16(%{{.*}})
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; CHECK-NEXT: movdqa %[[R0]], (%{{.*}})
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%a = load %i32vec7* %ap, align 16
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%b = load %i32vec7* %bp, align 16
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%x = add %i32vec7 %a, %b
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store %i32vec7 %x, %i32vec7* %ret, align 16
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ret void
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}
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%i32vec12 = type <12 x i32>
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define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) {
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; CHECK-LABEL: add12i32:
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; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 32(%{{.*}}), %[[R2:xmm[0-9]+]]
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; CHECK-NEXT: paddd (%{{.*}}), %[[R0]]
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; CHECK-NEXT: paddd 16(%{{.*}}), %[[R1]]
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; CHECK-NEXT: paddd 32(%{{.*}}), %[[R2]]
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; CHECK-NEXT: movdqa %[[R2]], 32(%{{.*}})
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; CHECK-NEXT: movdqa %[[R1]], 16(%{{.*}})
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; CHECK-NEXT: movdqa %[[R0]], (%{{.*}})
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%a = load %i32vec12* %ap, align 16
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%b = load %i32vec12* %bp, align 16
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%x = add %i32vec12 %a, %b
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store %i32vec12 %x, %i32vec12* %ret, align 16
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ret void
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}
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%i16vec3 = type <3 x i16>
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define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
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; CHECK-LABEL: add3i16:
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; CHECK: pmovzxwd (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: pmovzxwd (%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: paddd %[[R0]], %[[R1]]
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; CHECK-NEXT: movdqa %[[R1]], %[[R0]]
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; CHECK-NEXT: pshufb {{.*}}, %[[R0]]
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; CHECK-NEXT: pmovzxdq %[[R0]], %[[R0]]
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; CHECK-NEXT: pextrw $4, %[[R1]], 4(%{{.*}})
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; CHECK-NEXT: movd %[[R0]], (%{{.*}})
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%a = load %i16vec3* %ap, align 16
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%b = load %i16vec3* %bp, align 16
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%x = add %i16vec3 %a, %b
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store %i16vec3 %x, %i16vec3* %ret, align 16
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ret void
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}
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%i16vec4 = type <4 x i16>
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define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
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; CHECK-LABEL: add4i16:
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; CHECK: movq (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: movq (%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: paddw %[[R0]], %[[R1]]
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; CHECK-NEXT: movq %[[R1]], (%{{.*}})
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%a = load %i16vec4* %ap, align 16
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%b = load %i16vec4* %bp, align 16
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%x = add %i16vec4 %a, %b
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store %i16vec4 %x, %i16vec4* %ret, align 16
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ret void
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}
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%i16vec12 = type <12 x i16>
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define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind {
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; CHECK-LABEL: add12i16:
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; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: paddw (%{{.*}}), %[[R0]]
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; CHECK-NEXT: paddw 16(%{{.*}}), %[[R1]]
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; CHECK-NEXT: movq %[[R1]], 16(%{{.*}})
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; CHECK-NEXT: movdqa %[[R0]], (%{{.*}})
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%a = load %i16vec12* %ap, align 16
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%b = load %i16vec12* %bp, align 16
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%x = add %i16vec12 %a, %b
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store %i16vec12 %x, %i16vec12* %ret, align 16
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ret void
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}
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%i16vec18 = type <18 x i16>
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define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind {
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; CHECK-LABEL: add18i16:
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; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 32(%{{.*}}), %[[R2:xmm[0-9]+]]
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; CHECK-NEXT: paddw (%{{.*}}), %[[R0]]
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; CHECK-NEXT: paddw 16(%{{.*}}), %[[R1]]
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; CHECK-NEXT: paddw 32(%{{.*}}), %[[R2]]
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; CHECK-NEXT: movd %[[R2]], 32(%{{.*}})
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; CHECK-NEXT: movdqa %[[R1]], 16(%{{.*}})
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; CHECK-NEXT: movdqa %[[R0]], (%{{.*}})
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%a = load %i16vec18* %ap, align 16
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%b = load %i16vec18* %bp, align 16
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%x = add %i16vec18 %a, %b
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store %i16vec18 %x, %i16vec18* %ret, align 16
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ret void
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}
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%i8vec3 = type <3 x i8>
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define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
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; CHECK-LABEL: add3i8:
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; CHECK: pmovzxbd (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: pmovzxbd (%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: paddd %[[R0]], %[[R1]]
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; CHECK-NEXT: movdqa %[[R1]], %[[R0]]
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; CHECK-NEXT: pshufb {{.*}}, %[[R0]]
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; CHECK-NEXT: pmovzxwq %[[R0]], %[[R0]]
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; CHECK-NEXT: pextrb $8, %[[R1]], 2(%{{.*}})
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; CHECK-NEXT: movd %[[R0]], %e[[R2:[abcd]]]x
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; CHECK-NEXT: movw %[[R2]]x, (%{{.*}})
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%a = load %i8vec3* %ap, align 16
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%b = load %i8vec3* %bp, align 16
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%x = add %i8vec3 %a, %b
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store %i8vec3 %x, %i8vec3* %ret, align 16
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ret void
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}
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%i8vec31 = type <31 x i8>
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define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
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; CHECK-LABEL: add31i8:
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; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]
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; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]]
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; CHECK-NEXT: paddb (%{{.*}}), %[[R0]]
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; CHECK-NEXT: paddb 16(%{{.*}}), %[[R1]]
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; CHECK-NEXT: pextrb $14, %[[R1]], 30(%{{.*}})
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; CHECK-NEXT: pextrw $6, %[[R1]], 28(%{{.*}})
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; CHECK-NEXT: pextrd $2, %[[R1]], 24(%{{.*}})
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; CHECK-NEXT: movq %[[R1]], 16(%{{.*}})
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; CHECK-NEXT: movdqa %[[R0]], (%{{.*}})
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%a = load %i8vec31* %ap, align 16
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%b = load %i8vec31* %bp, align 16
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%x = add %i8vec31 %a, %b
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store %i8vec31 %x, %i8vec31* %ret, align 16
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ret void
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}
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%i8vec3pack = type { <3 x i8>, i8 }
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define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pack* %rot) nounwind {
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; CHECK-LABEL: rot:
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; CHECK: movdqa {{.*}}, %[[CONSTANT0:xmm[0-9]+]]
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; CHECK-NEXT: movdqa {{.*}}, %[[SHUFFLE_MASK:xmm[0-9]+]]
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; CHECK-NEXT: pshufb %[[SHUFFLE_MASK]], %[[CONSTANT0]]
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; CHECK-NEXT: pmovzxwq %[[CONSTANT0]], %[[CONSTANT0]]
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; CHECK-NEXT: movd %[[CONSTANT0]], %e[[R0:[abcd]]]x
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; CHECK-NEXT: movw %[[R0]]x, (%[[PTR0:.*]])
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; CHECK-NEXT: movb $-98, 2(%[[PTR0]])
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; CHECK-NEXT: movdqa {{.*}}, %[[CONSTANT1:xmm[0-9]+]]
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; CHECK-NEXT: pshufb %[[SHUFFLE_MASK]], %[[CONSTANT1]]
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; CHECK-NEXT: pmovzxwq %[[CONSTANT1]], %[[CONSTANT1]]
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; CHECK-NEXT: movd %[[CONSTANT1]], %e[[R1:[abcd]]]x
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; CHECK-NEXT: movw %[[R1]]x, (%[[PTR1:.*]])
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; CHECK-NEXT: movb $1, 2(%[[PTR1]])
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; CHECK-NEXT: pmovzxbd (%[[PTR0]]), %[[X0:xmm[0-9]+]]
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; CHECK-NEXT: pand {{.*}}, %[[X0]]
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; CHECK-NEXT: pextrd $1, %[[X0]], %e[[R0:[abcd]]]x
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; CHECK-NEXT: shrl %e[[R0]]x
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; CHECK-NEXT: movd %[[X0]], %e[[R1:[abcd]]]x
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; CHECK-NEXT: shrl %e[[R1]]x
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; CHECK-NEXT: movd %e[[R1]]x, %[[X1:xmm[0-9]+]]
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; CHECK-NEXT: pinsrd $1, %e[[R0]]x, %[[X1]]
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; CHECK-NEXT: pextrd $2, %[[X0]], %e[[R0:[abcd]]]x
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; CHECK-NEXT: shrl %e[[R0]]x
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; CHECK-NEXT: pinsrd $2, %e[[R0]]x, %[[X1]]
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; CHECK-NEXT: pextrd $3, %[[X0]], %e[[R0:[abcd]]]x
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; CHECK-NEXT: pinsrd $3, %e[[R0]]x, %[[X1]]
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; CHECK-NEXT: movdqa %[[X1]], %[[X2:xmm[0-9]+]]
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; CHECK-NEXT: pshufb %[[SHUFFLE_MASK]], %[[X2]]
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; CHECK-NEXT: pmovzxwq %[[X2]], %[[X3:xmm[0-9]+]]
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; CHECK-NEXT: pextrb $8, %[[X1]], 2(%{{.*}})
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; CHECK-NEXT: movd %[[X3]], %e[[R0:[abcd]]]x
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; CHECK-NEXT: movw %[[R0]]x, (%{{.*}})
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entry:
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%storetmp = bitcast %i8vec3pack* %X to <3 x i8>*
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store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
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%storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
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store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
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%tmp = load %i8vec3pack* %X
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%extractVec = extractvalue %i8vec3pack %tmp, 0
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%tmp2 = load %i8vec3pack* %rot
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%extractVec3 = extractvalue %i8vec3pack %tmp2, 0
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%shr = lshr <3 x i8> %extractVec, %extractVec3
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%storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
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store <3 x i8> %shr, <3 x i8>* %storetmp4
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ret void
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}
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