mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
fddb7667ca
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.4 KiB
TableGen
69 lines
2.4 KiB
TableGen
//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Get the target-independent interfaces which we are implementing...
|
|
//
|
|
include "llvm/Target/Target.td"
|
|
|
|
//Alpha is little endian
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Subtarget Features
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
|
|
"Enable CIX extentions">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaRegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Convention Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Schedule Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaSchedule.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaInstrInfo.td"
|
|
|
|
def AlphaInstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Alpha Processor Definitions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : Processor<"generic", Alpha21264Itineraries, []>;
|
|
def : Processor<"ev6" , Alpha21264Itineraries, []>;
|
|
def : Processor<"ev67" , Alpha21264Itineraries, [FeatureCIX]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// The Alpha Target
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
def Alpha : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = AlphaInstrInfo;
|
|
}
|