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41b3fe53ba
E.g. An interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
%v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.
E.g. An interleaved store (Factor = 3):
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.
Differential Revision: http://reviews.llvm.org/D10533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240751 91177308-0d34-0410-b5e6-96231b3b80d8
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| .. | ||
| CostTable.h | ||
| Target.td | ||
| TargetCallingConv.h | ||
| TargetCallingConv.td | ||
| TargetFrameLowering.h | ||
| TargetInstrInfo.h | ||
| TargetIntrinsicInfo.h | ||
| TargetItinerary.td | ||
| TargetLowering.h | ||
| TargetLoweringObjectFile.h | ||
| TargetMachine.h | ||
| TargetOpcodes.h | ||
| TargetOptions.h | ||
| TargetRecip.h | ||
| TargetRegisterInfo.h | ||
| TargetSchedule.td | ||
| TargetSelectionDAG.td | ||
| TargetSelectionDAGInfo.h | ||
| TargetSubtargetInfo.h | ||