Tim Northover 112102c7fe AArch64: disallow "fmov sD, #-0.0" during assembly. ... We weren't checking the sign of the floating point immediate before translating it to "fmov sD, wzr". Similarly for D-regs. Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's not a blessed alias (and I don't think it should be since people expect writing sD to zero out the high lanes, and there's no dD equivalent). So an error it is. rdar://20455398 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234372 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-07 22:49:47 +00:00
..
AArch64	AArch64: disallow "fmov sD, #-0.0" during assembly.	2015-04-07 22:49:47 +00:00
ARM	ARM: do not relax Thumb1 -> Thumb2 if only Thumb1 is available.	2015-04-06 18:44:42 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
ELF	Use a comma after the unique keyword.	2015-04-06 16:34:41 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-04-03 01:46:11 +00:00
Markup
Mips	[mips] [IAS] Allow .set assignments for already defined symbols.	2015-04-07 13:59:39 +00:00
PowerPC	[PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions	2015-03-28 19:42:41 +00:00
R600
Sparc
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	Fix the operand encoding in the test instruction.	2015-03-31 12:31:55 +00:00