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04bcc11905
derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227113 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
3.0 KiB
C++
99 lines
3.0 KiB
C++
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Hexagon specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonSubtarget.h"
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#include "Hexagon.h"
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#include "HexagonRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "HexagonGenSubtargetInfo.inc"
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static cl::opt<bool>
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EnableV3("enable-hexagon-v3", cl::Hidden,
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cl::desc("Enable Hexagon V3 instructions."));
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static cl::opt<bool>
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EnableMemOps(
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"enable-hexagon-memops",
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cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
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cl::desc(
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"Generate V4 MEMOP in code generation for Hexagon target"));
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static cl::opt<bool>
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DisableMemOps(
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"disable-hexagon-memops",
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cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
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cl::desc(
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"Do not generate V4 MEMOP in code generation for Hexagon target"));
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static cl::opt<bool>
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EnableIEEERndNear(
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"enable-hexagon-ieee-rnd-near",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Generate non-chopped conversion from fp to int."));
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HexagonSubtarget &
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HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
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// If the programmer has not specified a Hexagon version, default to -mv4.
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if (CPUString.empty())
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CPUString = "hexagonv4";
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if (CPUString == "hexagonv2") {
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HexagonArchVersion = V2;
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} else if (CPUString == "hexagonv3") {
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EnableV3 = true;
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HexagonArchVersion = V3;
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} else if (CPUString == "hexagonv4") {
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HexagonArchVersion = V4;
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} else if (CPUString == "hexagonv5") {
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HexagonArchVersion = V5;
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} else {
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llvm_unreachable("Unrecognized Hexagon processor version");
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}
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ParseSubtargetFeatures(CPUString, FS);
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return *this;
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}
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HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM)
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: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
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InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
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TSInfo(*TM.getDataLayout()), FrameLowering() {
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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// UseMemOps on by default unless disabled explicitly
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if (DisableMemOps)
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UseMemOps = false;
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else if (EnableMemOps)
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UseMemOps = true;
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else
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UseMemOps = false;
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if (EnableIEEERndNear)
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ModeIEEERndNear = true;
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else
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ModeIEEERndNear = false;
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}
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// Pin the vtable to this file.
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void HexagonSubtarget::anchor() {}
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