mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 22:29:56 +00:00
70968365db
vector type legalization strategies in a more fine grained manner, and change the legalization of several v1iN types and v1f32 to be widening rather than scalarization on AArch64. This fixes an assertion failure caused by scalarizing nodes like "v1i32 trunc v1i64". As v1i64 is legal it will fail to scalarize v1i32. This also provides a foundation for other targets to have more granular control over how vector types are legalized. Patch by Hao Liu, reviewed by Tim Northover. I'm committing it to allow some work to start taking place on top of this patch as it adds some really important hooks to the backend that I'd like to immediately start using. =] http://reviews.llvm.org/D4322 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212242 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
3.6 KiB
C++
85 lines
3.6 KiB
C++
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief SI DAG Lowering interface definition
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef SIISELLOWERING_H
|
|
#define SIISELLOWERING_H
|
|
|
|
#include "AMDGPUISelLowering.h"
|
|
#include "SIInstrInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
class SITargetLowering : public AMDGPUTargetLowering {
|
|
SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
|
|
SDValue Chain, unsigned Offset, bool Signed) const;
|
|
SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
|
|
SelectionDAG &DAG) const;
|
|
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
bool foldImm(SDValue &Operand, int32_t &Immediate,
|
|
bool &ScalarSlotUsed) const;
|
|
const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
|
|
const SDValue &Op) const;
|
|
bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
|
|
unsigned RegClass) const;
|
|
void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
|
|
unsigned RegClass, bool &ScalarSlotUsed) const;
|
|
|
|
SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
|
|
void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
|
|
MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
|
|
|
|
static SDValue performUCharToFloatCombine(SDNode *N,
|
|
DAGCombinerInfo &DCI);
|
|
|
|
public:
|
|
SITargetLowering(TargetMachine &tm);
|
|
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
|
|
bool *IsFast) const override;
|
|
|
|
TargetLoweringBase::LegalizeTypeAction
|
|
getPreferredVectorAction(EVT VT) const override;
|
|
|
|
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
|
Type *Ty) const override;
|
|
|
|
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
|
|
bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc DL, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
|
|
MachineBasicBlock * BB) const override;
|
|
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
|
|
MVT getScalarShiftAmountTy(EVT VT) const override;
|
|
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
|
|
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
|
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
|
SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
|
|
void AdjustInstrPostInstrSelection(MachineInstr *MI,
|
|
SDNode *Node) const override;
|
|
|
|
int32_t analyzeImmediate(const SDNode *N) const;
|
|
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
|
|
unsigned Reg, EVT VT) const override;
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif //SIISELLOWERING_H
|