Chad Rosier 67c325e9f0 [AArch64] Lower sdiv x, pow2 using add + select + shift. ... The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213758 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-23 14:57:52 +00:00
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CostTable.h
Target.td
TargetCallingConv.h
TargetCallingConv.td
TargetFrameLowering.h
TargetInstrInfo.h
TargetIntrinsicInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetItinerary.td
TargetJITInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetLibraryInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetLowering.h	[AArch64] Lower sdiv x, pow2 using add + select + shift.	2014-07-23 14:57:52 +00:00
TargetLoweringObjectFile.h	CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF	2014-07-14 22:57:27 +00:00
TargetMachine.h
TargetOpcodes.h
TargetOptions.h
TargetRegisterInfo.h	[RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the TargetRegisterInfo instead of the TargetSubtargetInfo.	2014-07-16 20:13:31 +00:00
TargetSchedule.td	Move Post RA Scheduling flag bit into SchedMachineModel	2014-07-15 22:39:58 +00:00
TargetSelectionDAG.td	Fix typos	2014-07-17 17:50:22 +00:00
TargetSelectionDAGInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetSubtargetInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00