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cc54e76cc6
assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen vreg. Other solutions might be preferable, such as: 1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently. 2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8
623 lines
22 KiB
C++
623 lines
22 KiB
C++
///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
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unsigned &Reg = ValueMap[V];
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if (Reg != 0)
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return Reg;
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MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
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if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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if (CI->getValue().getActiveBits() > 64)
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return 0;
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Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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} else if (isa<ConstantPointerNull>(V)) {
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Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
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if (!Reg) {
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const APFloat &Flt = CF->getValueAPF();
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MVT IntVT = TLI.getPointerTy();
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uint64_t x[2];
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uint32_t IntBitWidth = IntVT.getSizeInBits();
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if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
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APFloat::rmTowardZero) != APFloat::opOK)
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return 0;
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APInt IntVal(IntBitWidth, 2, x);
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unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
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ISD::Constant, IntVal.getZExtValue());
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if (IntegerReg == 0)
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return 0;
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Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
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if (Reg == 0)
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return 0;
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}
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} else if (isa<UndefValue>(V)) {
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Reg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
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}
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return Reg;
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}
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/// UpdateValueMap - Update the value map to include the new mapping for this
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/// instruction, or insert an extra copy to get the result in a previous
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/// determined register.
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/// NOTE: This is only necessary because we might select a block that uses
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/// a value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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void FastISel::UpdateValueMap(Instruction* I, unsigned Reg,
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DenseMap<const Value*, unsigned> &ValueMap) {
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if (!ValueMap.count(I))
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ValueMap[I] = Reg;
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else
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TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
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Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
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}
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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DenseMap<const Value*, unsigned> &ValueMap) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT))
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return false;
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unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// Check if the second operand is a constant and handle it appropriately.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
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unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, CI->getZExtValue());
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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}
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}
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// Check if the second operand is a constant float.
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if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
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unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, CF);
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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}
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}
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unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
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if (Op1 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// Now we have both operands in registers. Emit the instruction.
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unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, Op1);
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if (ResultReg == 0)
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return false;
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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}
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bool FastISel::SelectGetElementPtr(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap) {
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unsigned N = getRegForValue(I->getOperand(0), ValueMap);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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const Type *Ty = I->getOperand(0)->getType();
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MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
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for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
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OI != E; ++OI) {
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Value *Idx = *OI;
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if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
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unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
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if (Field) {
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// N = N + Offset
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uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
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// FIXME: This can be optimized by combining the add with a
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// subsequent one.
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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Ty = StTy->getElementType(Field);
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} else {
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Ty = cast<SequentialType>(Ty)->getElementType();
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// If this is a constant subscript, handle it quickly.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
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if (CI->getZExtValue() == 0) continue;
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uint64_t Offs =
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TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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continue;
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}
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = TD.getABITypeSize(Ty);
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unsigned IdxN = getRegForValue(Idx, ValueMap);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// If the index is smaller or larger than intptr_t, truncate or extend
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// it.
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MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
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if (IdxVT.bitsLT(VT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
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else if (IdxVT.bitsGT(VT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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if (ElementSize != 1) {
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IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, N, ValueMap);
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return true;
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}
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bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
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DenseMap<const Value*, unsigned> &ValueMap) {
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MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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MVT DstVT = TLI.getValueType(I->getType());
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if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
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DstVT == MVT::Other || !DstVT.isSimple() ||
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
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if (!InputReg)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
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DstVT.getSimpleVT(),
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Opcode,
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InputReg);
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if (!ResultReg)
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return false;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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}
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bool FastISel::SelectBitCast(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap) {
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// If the bitcast doesn't change the type, just use the operand value.
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if (I->getType() == I->getOperand(0)->getType()) {
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unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
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if (Reg == 0)
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return false;
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UpdateValueMap(I, Reg, ValueMap);
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return true;
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}
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// Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
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MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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MVT DstVT = TLI.getValueType(I->getType());
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if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
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DstVT == MVT::Other || !DstVT.isSimple() ||
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// First, try to perform the bitcast by inserting a reg-reg copy.
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unsigned ResultReg = 0;
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if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
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TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
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TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
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ResultReg = createResultReg(DstClass);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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Op0, DstClass, SrcClass);
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if (!InsertedCopy)
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ResultReg = 0;
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}
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// If the reg-reg copy failed, select a BIT_CONVERT opcode.
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if (!ResultReg)
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
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ISD::BIT_CONVERT, Op0);
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if (!ResultReg)
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return false;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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}
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BasicBlock::iterator
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FastISel::SelectInstructions(BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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DenseMap<const Value*, unsigned> &ValueMap,
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DenseMap<const BasicBlock*,
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MachineBasicBlock *> &MBBMap,
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MachineBasicBlock *mbb) {
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MBB = mbb;
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BasicBlock::iterator I = Begin;
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for (; I != End; ++I) {
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switch (I->getOpcode()) {
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case Instruction::Add: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::Sub: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::Mul: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::SDiv:
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if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
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case Instruction::UDiv:
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if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
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case Instruction::FDiv:
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if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
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case Instruction::SRem:
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if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
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case Instruction::URem:
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if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
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case Instruction::FRem:
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if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
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case Instruction::Shl:
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if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
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case Instruction::LShr:
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if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
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case Instruction::AShr:
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if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
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case Instruction::And:
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if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
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case Instruction::Or:
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if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
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case Instruction::Xor:
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if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
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case Instruction::GetElementPtr:
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if (!SelectGetElementPtr(I, ValueMap)) return I;
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break;
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case Instruction::Br: {
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BranchInst *BI = cast<BranchInst>(I);
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if (BI->isUnconditional()) {
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MachineFunction::iterator NextMBB =
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next(MachineFunction::iterator(MBB));
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BasicBlock *LLVMSucc = BI->getSuccessor(0);
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MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
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if (NextMBB != MF.end() && MSucc == NextMBB) {
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// The unconditional fall-through case, which needs no instructions.
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} else {
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// The unconditional branch case.
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TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
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}
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MBB->addSuccessor(MSucc);
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break;
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}
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// Conditional branches are not handed yet.
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// Halt "fast" selection and bail.
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return I;
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}
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case Instruction::PHI:
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// PHI nodes are already emitted.
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break;
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case Instruction::BitCast:
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if (!SelectBitCast(I, ValueMap)) return I; break;
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case Instruction::FPToSI:
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if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
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break;
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case Instruction::ZExt:
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if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
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break;
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case Instruction::SExt:
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if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
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break;
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case Instruction::Trunc:
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if (!SelectCast(I, ISD::TRUNCATE, ValueMap)) return I;
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break;
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case Instruction::SIToFP:
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if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
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break;
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case Instruction::IntToPtr: // Deliberate fall-through.
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case Instruction::PtrToInt: {
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MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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MVT DstVT = TLI.getValueType(I->getType());
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if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
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if (ValueMap[I->getOperand(0)]) {
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UpdateValueMap(I, ValueMap[I->getOperand(0)], ValueMap);
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break;
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} else
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// Unhandled operand
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return I;
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} else if (DstVT.bitsGT(SrcVT)) {
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if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
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break;
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} else {
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// TODO: Handle SrcVT > DstVT, where truncation is needed.
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return I;
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}
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}
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default:
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// Unhandled instruction. Halt "fast" selection and bail.
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return I;
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}
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}
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return I;
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}
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FastISel::FastISel(MachineFunction &mf)
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: MF(mf),
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MRI(mf.getRegInfo()),
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TM(mf.getTarget()),
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TD(*TM.getTargetData()),
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TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()) {
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}
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FastISel::~FastISel() {}
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unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
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return 0;
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}
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unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
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ISD::NodeType, unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
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ISD::NodeType, unsigned /*Op0*/,
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unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
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ISD::NodeType, uint64_t /*Imm*/) {
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return 0;
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|
}
|
|
|
|
unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
ISD::NodeType, ConstantFP * /*FPImm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
ISD::NodeType, unsigned /*Op0*/,
|
|
uint64_t /*Imm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
ISD::NodeType, unsigned /*Op0*/,
|
|
ConstantFP * /*FPImm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
ISD::NodeType,
|
|
unsigned /*Op0*/, unsigned /*Op1*/,
|
|
uint64_t /*Imm*/) {
|
|
return 0;
|
|
}
|
|
|
|
/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
|
|
/// to emit an instruction with an immediate operand using FastEmit_ri.
|
|
/// If that fails, it materializes the immediate into a register and try
|
|
/// FastEmit_rr instead.
|
|
unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
|
|
unsigned Op0, uint64_t Imm,
|
|
MVT::SimpleValueType ImmType) {
|
|
// First check if immediate type is legal. If not, we can't use the ri form.
|
|
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
|
|
if (ResultReg != 0)
|
|
return ResultReg;
|
|
unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
|
|
if (MaterialReg == 0)
|
|
return 0;
|
|
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
|
|
}
|
|
|
|
/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
|
|
/// to emit an instruction with a floating-point immediate operand using
|
|
/// FastEmit_rf. If that fails, it materializes the immediate into a register
|
|
/// and try FastEmit_rr instead.
|
|
unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
|
|
unsigned Op0, ConstantFP *FPImm,
|
|
MVT::SimpleValueType ImmType) {
|
|
// First check if immediate type is legal. If not, we can't use the rf form.
|
|
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
|
|
if (ResultReg != 0)
|
|
return ResultReg;
|
|
|
|
// Materialize the constant in a register.
|
|
unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
|
|
if (MaterialReg == 0) {
|
|
// If the target doesn't have a way to directly enter a floating-point
|
|
// value into a register, use an alternate approach.
|
|
// TODO: The current approach only supports floating-point constants
|
|
// that can be constructed by conversion from integer values. This should
|
|
// be replaced by code that creates a load from a constant-pool entry,
|
|
// which will require some target-specific work.
|
|
const APFloat &Flt = FPImm->getValueAPF();
|
|
MVT IntVT = TLI.getPointerTy();
|
|
|
|
uint64_t x[2];
|
|
uint32_t IntBitWidth = IntVT.getSizeInBits();
|
|
if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
|
|
APFloat::rmTowardZero) != APFloat::opOK)
|
|
return 0;
|
|
APInt IntVal(IntBitWidth, 2, x);
|
|
|
|
unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
|
|
ISD::Constant, IntVal.getZExtValue());
|
|
if (IntegerReg == 0)
|
|
return 0;
|
|
MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
|
|
ISD::SINT_TO_FP, IntegerReg);
|
|
if (MaterialReg == 0)
|
|
return 0;
|
|
}
|
|
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
|
|
}
|
|
|
|
unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
|
|
return MRI.createVirtualRegister(RC);
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass* RC) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, unsigned Op1) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, uint64_t Imm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, ConstantFP *FPImm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, unsigned Op1, uint64_t Imm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
uint64_t Imm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, II, ResultReg).addImm(Imm);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
|
|
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
|
|
const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
|
|
|
|
unsigned ResultReg = createResultReg(SRC);
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
|
|
return ResultReg;
|
|
}
|