Evan Cheng 11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the ... memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8		2010-08-11 06:22:01 +00:00
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ARMDisassembler.cpp	For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',	2010-04-20 17:28:50 +00:00
ARMDisassembler.h	Better error handling of invalid IT mask '0000', instead of just asserting.	2010-04-19 23:02:58 +00:00
ARMDisassemblerCore.cpp	- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the	2010-08-11 06:22:01 +00:00
ARMDisassemblerCore.h	Add a separate ARM instruction format for Saturate instructions.	2010-08-11 00:01:18 +00:00
Makefile	Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in	2010-04-07 20:53:12 +00:00
ThumbDisassemblerCore.h	Many Thumb2 instructions can reference the full ARM register set (i.e.,	2010-07-30 02:41:01 +00:00