mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ae43cab6ba
Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.6 KiB
LLVM
56 lines
1.6 KiB
LLVM
; RUN: llc < %s -O1 -mtriple=i386-apple-darwin -x86-asm-syntax=intel | FileCheck %s
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;
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; Interesting test case where %tmp1220 = xor i32 %tmp862, %tmp592 and
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; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after
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; DAGCombiner optimization pass. These are changed to undef and in turn
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; the successor shl(s) become shl undef, 1. This pattern then matches
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; shl x, 1 -> add x, x. add undef, undef doesn't guarantee the low
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; order bit is zero and is incorrect.
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;
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; See rdar://9453156 and rdar://9487392.
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;
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; Use intel syntax, or "shl" might hit "pushl".
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; CHECK-NOT: shl
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define i32 @foo(i8* %a0, i32* %a2) nounwind {
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entry:
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%tmp0 = alloca i8
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%tmp1 = alloca i32
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store i8 1, i8* %tmp0
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%tmp921.i7845 = load i8* %a0, align 1
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%tmp309 = xor i8 %tmp921.i7845, 104
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%tmp592 = zext i8 %tmp309 to i32
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%tmp862 = xor i32 1293461297, %tmp592
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%tmp1220 = xor i32 %tmp862, %tmp592
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%tmp1506 = shl i32 %tmp1220, 1
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%tmp1530 = sub i32 %tmp592, %tmp1506
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%tmp1557 = sub i32 %tmp1530, 542767629
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%tmp1607 = and i32 %tmp1557, 1
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store i32 %tmp1607, i32* %tmp1
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%tmp1634 = and i32 %tmp1607, 2080309246
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%tmp1676 = xor i32 %tmp1634, %tmp1530
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%tmp1618 = shl i32 %tmp1676, 1
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%tmp1645 = sub i32 %tmp862, %tmp1618
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%tmp1697 = and i32 %tmp1645, 1
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store i32 %tmp1697, i32* %a2
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ret i32 %tmp1607
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}
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; CHECK-NOT: shl
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; shl undef, 0 -> undef
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define i32 @foo2_undef() nounwind {
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entry:
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%tmp2 = shl i32 undef, 0;
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ret i32 %tmp2
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}
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; CHECK-NOT: shl
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; shl undef, x -> 0
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define i32 @foo1_undef(i32* %a0) nounwind {
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entry:
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%tmp1 = load i32* %a0, align 1
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%tmp2 = shl i32 undef, %tmp1;
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ret i32 %tmp2
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}
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