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e279f5953e
produces a 32-bit immediate which is consumed by the use. It tries to fold the immediate by breaking it into two parts and fold them into the immmediate fields of two uses. e.g movw r2, #40885 movt r3, #46540 add r0, r0, r3 => add.w r0, r0, #3019898880 add.w r0, r0, #30146560 ; However, this transformation is incorrect if the user produces a flag. e.g. movw r2, #40885 movt r3, #46540 adds r0, r0, r3 => add.w r0, r0, #3019898880 adds.w r0, r0, #30146560 Note the adds.w may not set the carry flag even if the original sequence would. rdar://11116189 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153484 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
1.1 KiB
LLVM
34 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s
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; ARM has a peephole optimization which looks for a def / use pair. The def
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; produces a 32-bit immediate which is consumed by the use. It tries to
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; fold the immediate by breaking it into two parts and fold them into the
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; immmediate fields of two uses. e.g
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; movw r2, #40885
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; movt r3, #46540
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; add r0, r0, r3
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; =>
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; add.w r0, r0, #3019898880
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; add.w r0, r0, #30146560
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;
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; However, this transformation is incorrect if the user produces a flag. e.g.
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; movw r2, #40885
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; movt r3, #46540
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; adds r0, r0, r3
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; =>
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; add.w r0, r0, #3019898880
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; adds.w r0, r0, #30146560
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; Note the adds.w may not set the carry flag even if the original sequence
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; would.
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;
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; rdar://11116189
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define i64 @t(i64 %aInput) nounwind {
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; CHECK: t:
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; CHECK: movs [[REG:(r[0-9]+)]], #0
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; CHECK: movt [[REG]], #46540
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; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
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%1 = mul i64 %aInput, 1000000
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%2 = add i64 %1, -7952618389194932224
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ret i64 %2
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}
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