mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-23 15:29:51 +00:00
5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
255 lines
7.8 KiB
LLVM
255 lines
7.8 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE
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; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
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define void @call0() nounwind {
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entry:
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ret void
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}
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define void @foo0() nounwind {
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entry:
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; CHECK-LABEL: foo0
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; CHECK: bl _call0
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; LARGE-LABEL: foo0
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; LARGE: adrp [[REG0:x[0-9]+]], _call0@GOTPAGE
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; LARGE: ldr [[REG1:x[0-9]+]], {{\[}}[[REG0]], _call0@GOTPAGEOFF{{\]}}
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; LARGE-NEXT: blr [[REG1]]
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call void @call0()
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ret void
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}
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define i32 @call1(i32 %a) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%tmp = load i32* %a.addr, align 4
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ret i32 %tmp
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}
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define i32 @foo1(i32 %a) nounwind {
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entry:
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; CHECK-LABEL: foo1
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; CHECK: stur w0, [x29, #-4]
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; CHECK-NEXT: ldur w0, [x29, #-4]
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; CHECK-NEXT: bl _call1
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%tmp = load i32* %a.addr, align 4
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%call = call i32 @call1(i32 %tmp)
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ret i32 %call
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}
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define i32 @sext_(i8 %a, i16 %b) nounwind {
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entry:
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; CHECK-LABEL: sext_
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; CHECK: sxtb w0, w0
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; CHECK: sxth w1, w1
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; CHECK: bl _foo_sext_
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call void @foo_sext_(i8 signext %a, i16 signext %b)
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ret i32 0
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}
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declare void @foo_sext_(i8 %a, i16 %b)
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define i32 @zext_(i8 %a, i16 %b) nounwind {
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entry:
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; CHECK-LABEL: zext_
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; CHECK: uxtb w0, w0
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; CHECK: uxth w1, w1
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call void @foo_zext_(i8 zeroext %a, i16 zeroext %b)
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ret i32 0
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}
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declare void @foo_zext_(i8 %a, i16 %b)
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define i32 @t1(i32 %argc, i8** nocapture %argv) {
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entry:
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; CHECK-LABEL: @t1
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; The last parameter will be passed on stack via i8.
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; CHECK: strb w{{[0-9]+}}, [sp]
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; CHECK: bl _bar
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%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70, i8 zeroext 28, i8 zeroext 39, i8 zeroext -41)
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ret i32 0
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}
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declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext)
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; Test materialization of integers. Target-independent selector handles this.
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define i32 @t2() {
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entry:
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; CHECK-LABEL: t2
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; CHECK: mov [[REG1:x[0-9]+]], xzr
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; CHECK: orr w1, wzr, #0xfffffff8
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; CHECK: orr [[REG2:w[0-9]+]], wzr, #0x3ff
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; CHECK: orr [[REG3:w[0-9]+]], wzr, #0x2
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; CHECK: mov [[REG4:w[0-9]+]], wzr
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; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x1
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; CHECK: mov x0, [[REG1]]
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; CHECK: uxth w2, [[REG2]]
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; CHECK: sxtb w3, [[REG3]]
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; CHECK: and w4, [[REG4]], #0x1
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; CHECK: and w5, [[REG5]], #0x1
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; CHECK: bl _func2
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%call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)
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ret i32 0
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}
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declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext, i1 zeroext)
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declare void @callee_b0f(i8 %bp10, i8 %bp11, i8 %bp12, i8 %bp13, i8 %bp14, i8 %bp15, i8 %bp17, i8 %bp18, i8 %bp19)
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define void @caller_b1f() {
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entry:
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; CHECK-BE-LABEL: caller_b1f
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; CHECK-BE: strb w{{.*}}, [sp, #7]
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call void @callee_b0f(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 42)
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ret void
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}
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define zeroext i1 @call_arguments1(i1 %a1, i1 %a2, i1 %a3, i1 %a4, i1 %a5, i1 %a6, i1 %a7, i1 %a8) {
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; CHECK-LABEL: call_arguments1
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; CHECK: and {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, w2, w3
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; CHECK-NEXT: and {{w[0-9]+}}, w4, w5
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; CHECK-NEXT: and {{w[0-9]+}}, w6, w7
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%1 = and i1 %a1, %a2
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%2 = and i1 %a3, %a4
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%3 = and i1 %a5, %a6
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%4 = and i1 %a7, %a8
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%5 = and i1 %1, %2
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%6 = and i1 %3, %4
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%7 = and i1 %5, %6
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ret i1 %7
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}
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define i32 @call_arguments2(i8 zeroext %a1, i8 zeroext %a2, i8 zeroext %a3, i8 zeroext %a4, i8 signext %a5, i8 signext %a6, i8 signext %a7, i8 signext %a8) {
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; CHECK-LABEL: call_arguments2
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; CHECK: add {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: add {{w[0-9]+}}, w2, w3
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; CHECK-NEXT: add {{w[0-9]+}}, w4, w5
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; CHECK-NEXT: add {{w[0-9]+}}, w6, w7
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%a1z = zext i8 %a1 to i32
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%a2z = zext i8 %a2 to i32
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%a3z = zext i8 %a3 to i32
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%a4z = zext i8 %a4 to i32
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%a5s = sext i8 %a5 to i32
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%a6s = sext i8 %a6 to i32
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%a7s = sext i8 %a7 to i32
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%a8s = sext i8 %a8 to i32
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%1 = add i32 %a1z, %a2z
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%2 = add i32 %a3z, %a4z
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%3 = add i32 %a5s, %a6s
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%4 = add i32 %a7s, %a8s
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%5 = add i32 %1, %2
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%6 = add i32 %3, %4
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%7 = add i32 %5, %6
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ret i32 %7
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}
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define i32 @call_arguments3(i16 zeroext %a1, i16 zeroext %a2, i16 zeroext %a3, i16 zeroext %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i16 signext %a8) {
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; CHECK-LABEL: call_arguments3
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; CHECK: add {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: add {{w[0-9]+}}, w2, w3
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; CHECK-NEXT: add {{w[0-9]+}}, w4, w5
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; CHECK-NEXT: add {{w[0-9]+}}, w6, w7
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%a1z = zext i16 %a1 to i32
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%a2z = zext i16 %a2 to i32
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%a3z = zext i16 %a3 to i32
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%a4z = zext i16 %a4 to i32
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%a5s = sext i16 %a5 to i32
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%a6s = sext i16 %a6 to i32
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%a7s = sext i16 %a7 to i32
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%a8s = sext i16 %a8 to i32
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%1 = add i32 %a1z, %a2z
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%2 = add i32 %a3z, %a4z
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%3 = add i32 %a5s, %a6s
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%4 = add i32 %a7s, %a8s
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%5 = add i32 %1, %2
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%6 = add i32 %3, %4
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%7 = add i32 %5, %6
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ret i32 %7
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}
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define i32 @call_arguments4(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) {
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; CHECK-LABEL: call_arguments4
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; CHECK: add {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: add {{w[0-9]+}}, w2, w3
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; CHECK-NEXT: add {{w[0-9]+}}, w4, w5
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; CHECK-NEXT: add {{w[0-9]+}}, w6, w7
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%1 = add i32 %a1, %a2
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%2 = add i32 %a3, %a4
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%3 = add i32 %a5, %a6
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%4 = add i32 %a7, %a8
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%5 = add i32 %1, %2
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%6 = add i32 %3, %4
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%7 = add i32 %5, %6
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ret i32 %7
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}
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define i64 @call_arguments5(i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, i64 %a8) {
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; CHECK-LABEL: call_arguments5
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; CHECK: add {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: add {{x[0-9]+}}, x2, x3
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; CHECK-NEXT: add {{x[0-9]+}}, x4, x5
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; CHECK-NEXT: add {{x[0-9]+}}, x6, x7
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%1 = add i64 %a1, %a2
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%2 = add i64 %a3, %a4
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%3 = add i64 %a5, %a6
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%4 = add i64 %a7, %a8
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%5 = add i64 %1, %2
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%6 = add i64 %3, %4
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%7 = add i64 %5, %6
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ret i64 %7
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}
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define float @call_arguments6(float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8) {
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; CHECK-LABEL: call_arguments6
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; CHECK: fadd {{s[0-9]+}}, s0, s1
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; CHECK-NEXT: fadd {{s[0-9]+}}, s2, s3
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; CHECK-NEXT: fadd {{s[0-9]+}}, s4, s5
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; CHECK-NEXT: fadd {{s[0-9]+}}, s6, s7
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%1 = fadd float %a1, %a2
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%2 = fadd float %a3, %a4
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%3 = fadd float %a5, %a6
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%4 = fadd float %a7, %a8
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%5 = fadd float %1, %2
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%6 = fadd float %3, %4
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%7 = fadd float %5, %6
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ret float %7
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}
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define double @call_arguments7(double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7, double %a8) {
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; CHECK-LABEL: call_arguments7
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; CHECK: fadd {{d[0-9]+}}, d0, d1
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; CHECK-NEXT: fadd {{d[0-9]+}}, d2, d3
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; CHECK-NEXT: fadd {{d[0-9]+}}, d4, d5
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; CHECK-NEXT: fadd {{d[0-9]+}}, d6, d7
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%1 = fadd double %a1, %a2
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%2 = fadd double %a3, %a4
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%3 = fadd double %a5, %a6
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%4 = fadd double %a7, %a8
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%5 = fadd double %1, %2
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%6 = fadd double %3, %4
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%7 = fadd double %5, %6
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ret double %7
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}
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define i64 @call_arguments8(i32 %a1, i64 %a2, i32 %a3, i64 %a4) {
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; CHECK-LABEL: call_arguments8
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; CHECK: ubfx [[REG1:x[0-9]+]], {{x[0-9]+}}, #0, #32
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; CHECK: ubfx [[REG2:x[0-9]+]], {{x[0-9]+}}, #0, #32
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; CHECK: add {{x[0-9]+}}, [[REG1]], x1
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; CHECK-NEXT: add {{x[0-9]+}}, [[REG2]], x3
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%aa1 = zext i32 %a1 to i64
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%aa3 = zext i32 %a3 to i64
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%1 = add i64 %aa1, %a2
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%2 = add i64 %aa3, %a4
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%3 = add i64 %1, %2
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ret i64 %3
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}
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define void @call_arguments9(i8 %a1, i16 %a2, i32 %a3, i64 %a4, float %a5, double %a6, i64 %a7, double %a8) {
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; CHECK-LABEL: call_arguments9
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ret void
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}
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