1
0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-30 02:32:08 +00:00
llvm-6502/test/CodeGen/ARM/copy-paired-reg.ll
JF Bastien 1b6f5a29ab Fix ARM paired GPR COPY lowering
ARM paired GPR COPY was being lowered to two MOVr without CC. This
patch puts the CC back.

My test is a reduction of the case where I encountered the issue,
64-bit atomics use paired GPRs.

The issue only occurs with selectionDAG, FastISel doesn't encounter it
so I didn't bother calling it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 23:33:03 +00:00

18 lines
431 B
LLVM

; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -verify-machineinstrs
define void @f() {
%a = alloca i8, i32 8, align 8
%b = alloca i8, i32 8, align 8
%c = bitcast i8* %a to i64*
%d = bitcast i8* %b to i64*
store atomic i64 0, i64* %c seq_cst, align 8
store atomic i64 0, i64* %d seq_cst, align 8
%e = load atomic i64* %d seq_cst, align 8
ret void
}