mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
128a7a96f0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4816 91177308-0d34-0410-b5e6-96231b3b80d8
505 lines
17 KiB
C++
505 lines
17 KiB
C++
//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "Support/Statistic.h"
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namespace {
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struct Printer : public FunctionPass {
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TargetMachine &TM;
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std::ostream &O;
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Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
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bool runOnFunction(Function &F);
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};
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}
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/// createX86CodePrinterPass - Print out the specified machine code function to
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/// the specified stream. This function should work regardless of whether or
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/// not the function is in SSA form or not.
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///
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Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
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return new Printer(TM, O);
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}
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnFunction (Function & F)
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{
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static unsigned bbnumber = 0;
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MachineFunction & MF = MachineFunction::get (&F);
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const MachineInstrInfo & MII = TM.getInstrInfo ();
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O << "; x86 printing only sorta implemented so far!\n";
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// Print out labels for the function.
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O << "\t.globl\t" << F.getName () << "\n";
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O << "\t.type\t" << F.getName () << ", @function\n";
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O << F.getName () << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
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bb_i != bb_e; ++bb_i)
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{
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// Print a label for the basic block.
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O << ".BB" << bbnumber++ << ":\n";
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for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
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bb_i->end (); i_i != i_e; ++i_i)
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{
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// Print the assembly for the instruction.
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O << "\t";
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MII.print(*i_i, O, TM);
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}
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}
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// We didn't modify anything.
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return false;
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}
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static bool isReg(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_VirtualRegister ||
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MO.getType() == MachineOperand::MO_MachineRegister;
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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static bool isScale(const MachineOperand &MO) {
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return isImmediate(MO) &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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return Op+4 <= MI->getNumOperands() &&
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isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
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isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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const MRegisterInfo &RI) {
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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}
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static void printMemReference(std::ostream &O, const MachineInstr *MI,
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unsigned Op, const MRegisterInfo &RI) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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const MachineOperand &BaseReg = MI->getOperand(Op);
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const MachineOperand &Scale = MI->getOperand(Op+1);
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &Disp = MI->getOperand(Op+3);
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O << "[";
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOp(O, BaseReg, RI);
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (IndexReg.getImmedValue() != 1)
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O << IndexReg.getImmedValue() << "*";
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printOp(O, IndexReg, RI);
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NeedPlus = true;
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}
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if (Disp.getImmedValue()) {
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if (NeedPlus) O << " + ";
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printOp(O, Disp, RI);
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}
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O << "]";
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}
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static inline void toHexDigit(std::ostream &O, unsigned char V) {
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if (V >= 10)
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O << (char)('A'+V-10);
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else
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O << (char)('0'+V);
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}
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static std::ostream &toHex(std::ostream &O, unsigned char V) {
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toHexDigit(O, V >> 4);
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toHexDigit(O, V & 0xF);
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return O;
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}
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static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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toHex(O, Val) << " ";
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Val >>= 8;
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}
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return O;
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}
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namespace N86 { // Native X86 Register numbers...
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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static unsigned getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
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case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
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case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
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case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
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default:
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assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
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"Unknown physical register!");
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DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
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<< " correctly yet!\n");
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return 0;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
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unsigned RegOpcodeField) {
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toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg)));
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}
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inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
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unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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toHex(O, ModRMByte(SS, Index, Base));
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}
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
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unsigned Op, unsigned RegOpcodeField) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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const MachineOperand &BaseReg = MI->getOperand(Op);
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const MachineOperand &Scale = MI->getOperand(Op+1);
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &Disp = MI->getOperand(Op+3);
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
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if (BaseReg.getReg() == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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toHex(O, ModRMByte(0, RegOpcodeField, 5));
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emitConstant(O, Disp.getImmedValue(), 4);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding... [REG+disp8]
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toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(O, Disp.getImmedValue(), 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(O, Disp.getImmedValue(), 4);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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if (BaseReg.getReg() == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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toHex(O, ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (Disp.getImmedValue() == 0) {
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// Emit no displacement ModR/M byte
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toHex(O, ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding...
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toHex(O, ModRMByte(1, RegOpcodeField, 4));
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} else {
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// Emit the normal disp32 encoding...
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toHex(O, ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImmedValue()];
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if (BaseReg.getReg() == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
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emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (Disp.getImmedValue() != 0 || ForceDisp32) {
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if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
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emitConstant(O, Disp.getImmedValue(), 1);
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else
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emitConstant(O, Disp.getImmedValue(), 4);
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}
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}
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}
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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unsigned Opcode = MI->getOpcode();
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const MachineInstrDescriptor &Desc = get(Opcode);
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// Print instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
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if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::OtherFrm:
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O << "\t\t\t";
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O << "-"; MI->print(O, TM);
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode));
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " ";
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i) O << ", ";
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printOp(O, MI->getOperand(i), RI);
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}
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O << "\n";
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return;
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case X86II::AddRegFrm: {
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// There are currently two forms of acceptable AddRegFrm instructions.
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// Either the instruction JUST takes a single register (like inc, dec, etc),
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// or it takes a register and an immediate of the same size as the register
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// (move immediate f.e.).
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 1 ||
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(MI->getNumOperands() == 2 && isImmediate(MI->getOperand(1)))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
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if (MI->getNumOperands() == 2) {
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unsigned Size = 4;
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emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
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}
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (MI->getNumOperands() == 2) {
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O << ", ";
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printOp(O, MI->getOperand(1), RI);
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}
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O << "\n";
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return;
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}
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case X86II::MRMDestReg: {
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// There are two acceptable forms of MRMDestReg instructions, those with 3
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// and 2 operands:
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
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isReg(MI->getOperand(MI->getNumOperands()-1))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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unsigned ModRMReg = MI->getOperand(0).getReg();
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unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
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emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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}
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case X86II::MRMDestMem: {
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// These instructions are the same as MRMDestReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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emitMemModRMByte(O, MI, 0, getX86RegNum(MI->getOperand(4).getReg()));
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " <SIZE> PTR ";
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printMemReference(O, MI, 0, RI);
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcReg: {
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// There is a two forms that are acceptable for MRMSrcReg instructions,
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// those with 3 and 2 operands:
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//
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// 3 Operands: in this form, the last register (the second input) is the
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// ModR/M input. The first two operands should be the same, post register
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// allocation. This is for things like: add r32, r/m32
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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isReg(MI->getOperand(1)) &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
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unsigned ExtraReg = MI->getOperand(0).getReg();
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emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcMem: {
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
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isMem(MI, 2))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 2+4 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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unsigned ExtraReg = MI->getOperand(0).getReg();
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emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
|
|
|
|
O << "\n\t\t\t\t";
|
|
O << getName(MI->getOpCode()) << " ";
|
|
printOp(O, MI->getOperand(0), RI);
|
|
O << ", <SIZE> PTR ";
|
|
printMemReference(O, MI, MI->getNumOperands()-4, RI);
|
|
O << "\n";
|
|
return;
|
|
}
|
|
|
|
case X86II::MRMS0r: case X86II::MRMS1r:
|
|
case X86II::MRMS2r: case X86II::MRMS3r:
|
|
case X86II::MRMS4r: case X86II::MRMS5r:
|
|
case X86II::MRMS6r: case X86II::MRMS7r: {
|
|
unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
|
|
|
|
// In this form, the following are valid formats:
|
|
// 1. sete r
|
|
// 2. shl rdest, rinput <implicit CL or 1>
|
|
// 3. sbb rdest, rinput, immediate [rdest = rinput]
|
|
//
|
|
assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
|
|
isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
|
|
assert((MI->getNumOperands() < 2 || isReg(MI->getOperand(1))) &&
|
|
"Bad MRMSxR format!");
|
|
assert((MI->getNumOperands() < 3 || isImmediate(MI->getOperand(2))) &&
|
|
"Bad MRMSxR format!");
|
|
|
|
if (MI->getNumOperands() > 1 &&
|
|
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
|
O << "**";
|
|
|
|
toHex(O, getBaseOpcodeFor(Opcode)) << " ";
|
|
emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
|
|
|
|
if (MI->getNumOperands() == 3) {
|
|
unsigned Size = 4;
|
|
emitConstant(O, MI->getOperand(2).getImmedValue(), Size);
|
|
}
|
|
|
|
O << "\n\t\t\t\t";
|
|
O << getName(MI->getOpCode()) << " ";
|
|
printOp(O, MI->getOperand(0), RI);
|
|
if (MI->getNumOperands() == 3) {
|
|
O << ", ";
|
|
printOp(O, MI->getOperand(2), RI);
|
|
}
|
|
O << "\n";
|
|
|
|
return;
|
|
}
|
|
|
|
default:
|
|
O << "\t\t\t-"; MI->print(O, TM); break;
|
|
}
|
|
}
|