mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
c2884320fe
This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
224 lines
8.1 KiB
LLVM
224 lines
8.1 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
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@var_8bit = global i8 0
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@var_16bit = global i16 0
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@var_32bit = global i32 0
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@var_64bit = global i64 0
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@var_float = global float 0.0
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@var_double = global double 0.0
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@varptr = global i8* null
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define void @ldst_8bit() {
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; CHECK-LABEL: ldst_8bit:
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; No architectural support for loads to 16-bit or 8-bit since we
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; promote i8 during lowering.
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%addr_8bit = load i8** @varptr
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; match a sign-extending load 8-bit -> 32-bit
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%addr_sext32 = getelementptr i8* %addr_8bit, i64 -256
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%val8_sext32 = load volatile i8* %addr_sext32
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%val32_signed = sext i8 %val8_sext32 to i32
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store volatile i32 %val32_signed, i32* @var_32bit
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; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
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; match a zero-extending load volatile 8-bit -> 32-bit
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%addr_zext32 = getelementptr i8* %addr_8bit, i64 -12
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%val8_zext32 = load volatile i8* %addr_zext32
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%val32_unsigned = zext i8 %val8_zext32 to i32
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store volatile i32 %val32_unsigned, i32* @var_32bit
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; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12]
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; match an any-extending load volatile 8-bit -> 32-bit
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%addr_anyext = getelementptr i8* %addr_8bit, i64 -1
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%val8_anyext = load volatile i8* %addr_anyext
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%newval8 = add i8 %val8_anyext, 1
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store volatile i8 %newval8, i8* @var_8bit
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; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
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; match a sign-extending load volatile 8-bit -> 64-bit
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%addr_sext64 = getelementptr i8* %addr_8bit, i64 -5
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%val8_sext64 = load volatile i8* %addr_sext64
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%val64_signed = sext i8 %val8_sext64 to i64
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store volatile i64 %val64_signed, i64* @var_64bit
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; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
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; match a zero-extending load volatile 8-bit -> 64-bit.
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; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
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; of x0 so it's identical to load volatileing to 32-bits.
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%addr_zext64 = getelementptr i8* %addr_8bit, i64 -9
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%val8_zext64 = load volatile i8* %addr_zext64
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%val64_unsigned = zext i8 %val8_zext64 to i64
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store volatile i64 %val64_unsigned, i64* @var_64bit
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; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9]
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; truncating store volatile 32-bits to 8-bits
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%addr_trunc32 = getelementptr i8* %addr_8bit, i64 -256
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%val32 = load volatile i32* @var_32bit
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%val8_trunc32 = trunc i32 %val32 to i8
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store volatile i8 %val8_trunc32, i8* %addr_trunc32
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; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
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; truncating store volatile 64-bits to 8-bits
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%addr_trunc64 = getelementptr i8* %addr_8bit, i64 -1
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%val64 = load volatile i64* @var_64bit
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%val8_trunc64 = trunc i64 %val64 to i8
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store volatile i8 %val8_trunc64, i8* %addr_trunc64
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; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
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ret void
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}
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define void @ldst_16bit() {
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; CHECK-LABEL: ldst_16bit:
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; No architectural support for loads to 16-bit or 16-bit since we
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; promote i16 during lowering.
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%addr_8bit = load i8** @varptr
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; match a sign-extending load 16-bit -> 32-bit
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%addr8_sext32 = getelementptr i8* %addr_8bit, i64 -256
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%addr_sext32 = bitcast i8* %addr8_sext32 to i16*
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%val16_sext32 = load volatile i16* %addr_sext32
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%val32_signed = sext i16 %val16_sext32 to i32
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store volatile i32 %val32_signed, i32* @var_32bit
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; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
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; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned.
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%addr8_zext32 = getelementptr i8* %addr_8bit, i64 15
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%addr_zext32 = bitcast i8* %addr8_zext32 to i16*
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%val16_zext32 = load volatile i16* %addr_zext32
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%val32_unsigned = zext i16 %val16_zext32 to i32
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store volatile i32 %val32_unsigned, i32* @var_32bit
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; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15]
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; match an any-extending load volatile 16-bit -> 32-bit
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%addr8_anyext = getelementptr i8* %addr_8bit, i64 -1
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%addr_anyext = bitcast i8* %addr8_anyext to i16*
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%val16_anyext = load volatile i16* %addr_anyext
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%newval16 = add i16 %val16_anyext, 1
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store volatile i16 %newval16, i16* @var_16bit
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; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
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; match a sign-extending load volatile 16-bit -> 64-bit
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%addr8_sext64 = getelementptr i8* %addr_8bit, i64 -5
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%addr_sext64 = bitcast i8* %addr8_sext64 to i16*
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%val16_sext64 = load volatile i16* %addr_sext64
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%val64_signed = sext i16 %val16_sext64 to i64
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store volatile i64 %val64_signed, i64* @var_64bit
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; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
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; match a zero-extending load volatile 16-bit -> 64-bit.
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; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
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; of x0 so it's identical to load volatileing to 32-bits.
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%addr8_zext64 = getelementptr i8* %addr_8bit, i64 9
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%addr_zext64 = bitcast i8* %addr8_zext64 to i16*
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%val16_zext64 = load volatile i16* %addr_zext64
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%val64_unsigned = zext i16 %val16_zext64 to i64
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store volatile i64 %val64_unsigned, i64* @var_64bit
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; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9]
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; truncating store volatile 32-bits to 16-bits
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%addr8_trunc32 = getelementptr i8* %addr_8bit, i64 -256
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%addr_trunc32 = bitcast i8* %addr8_trunc32 to i16*
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%val32 = load volatile i32* @var_32bit
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%val16_trunc32 = trunc i32 %val32 to i16
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store volatile i16 %val16_trunc32, i16* %addr_trunc32
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; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
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; truncating store volatile 64-bits to 16-bits
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%addr8_trunc64 = getelementptr i8* %addr_8bit, i64 -1
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%addr_trunc64 = bitcast i8* %addr8_trunc64 to i16*
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%val64 = load volatile i64* @var_64bit
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%val16_trunc64 = trunc i64 %val64 to i16
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store volatile i16 %val16_trunc64, i16* %addr_trunc64
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; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
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ret void
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}
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define void @ldst_32bit() {
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; CHECK-LABEL: ldst_32bit:
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%addr_8bit = load i8** @varptr
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; Straight 32-bit load/store
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%addr32_8_noext = getelementptr i8* %addr_8bit, i64 1
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%addr32_noext = bitcast i8* %addr32_8_noext to i32*
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%val32_noext = load volatile i32* %addr32_noext
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store volatile i32 %val32_noext, i32* %addr32_noext
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; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
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; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
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; Zero-extension to 64-bits
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%addr32_8_zext = getelementptr i8* %addr_8bit, i64 -256
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%addr32_zext = bitcast i8* %addr32_8_zext to i32*
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%val32_zext = load volatile i32* %addr32_zext
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%val64_unsigned = zext i32 %val32_zext to i64
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store volatile i64 %val64_unsigned, i64* @var_64bit
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; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
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; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit]
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; Sign-extension to 64-bits
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%addr32_8_sext = getelementptr i8* %addr_8bit, i64 -12
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%addr32_sext = bitcast i8* %addr32_8_sext to i32*
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%val32_sext = load volatile i32* %addr32_sext
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%val64_signed = sext i32 %val32_sext to i64
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store volatile i64 %val64_signed, i64* @var_64bit
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; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12]
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; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit]
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; Truncation from 64-bits
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%addr64_8_trunc = getelementptr i8* %addr_8bit, i64 255
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%addr64_trunc = bitcast i8* %addr64_8_trunc to i64*
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%addr32_8_trunc = getelementptr i8* %addr_8bit, i64 -20
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%addr32_trunc = bitcast i8* %addr32_8_trunc to i32*
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%val64_trunc = load volatile i64* %addr64_trunc
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%val32_trunc = trunc i64 %val64_trunc to i32
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store volatile i32 %val32_trunc, i32* %addr32_trunc
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; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255]
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; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #-20]
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ret void
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}
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define void @ldst_float() {
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; CHECK-LABEL: ldst_float:
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%addr_8bit = load i8** @varptr
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%addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
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%addrfp = bitcast i8* %addrfp_8 to float*
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%valfp = load volatile float* %addrfp
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; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
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; CHECK-NOFP-NOT: ldur {{s[0-9]+}},
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store volatile float %valfp, float* %addrfp
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; CHECK: stur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
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; CHECK-NOFP-NOT: stur {{s[0-9]+}},
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ret void
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}
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define void @ldst_double() {
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; CHECK-LABEL: ldst_double:
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%addr_8bit = load i8** @varptr
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%addrfp_8 = getelementptr i8* %addr_8bit, i64 4
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%addrfp = bitcast i8* %addrfp_8 to double*
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%valfp = load volatile double* %addrfp
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; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
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; CHECK-NOFP-NOT: ldur {{d[0-9]+}},
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store volatile double %valfp, double* %addrfp
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; CHECK: stur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
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; CHECK-NOFP-NOT: stur {{d[0-9]+}},
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ret void
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}
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