Evan Cheng 12c24690c7 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-14 22:54:52 +00:00
..
Analysis	Add support to preserve type info for the variables that are removed by the optimizer.	2010-05-14 21:01:35 +00:00
Archive
AsmParser
Bitcode
CodeGen	Fast ISel trivially coalesces away no-op casts, so check for this when	2010-05-14 22:53:18 +00:00
CompilerDriver
ExecutionEngine
Linker
MC	MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be	2010-05-14 18:53:40 +00:00
Support
System
Target	Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.	2010-05-14 22:54:52 +00:00
Transforms	Remove heinous tabs.	2010-05-13 06:45:13 +00:00
VMCore	Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.	2010-05-13 23:55:47 +00:00
Makefile