llvm-6502/test/MC/Mips
Jack Carter 77217229ba Mips specific standalone assembler addressing mode %hi and %lo.
The constructs %hi() and %lo() represent the high and low 16 
bits of the address. 
Because the 16 bit offset field of an LW instruction is 
interpreted as signed, if bit 15 of the low part is 1 then the 
low part will act as a negative and 1 needs to be added to the 
high part.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175707 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 02:09:31 +00:00
..
do_switch.ll
ef_frame.ll
elf_basic.s
elf_eflags.ll ELF symbol table field st_other support, 2013-02-19 22:29:00 +00:00
elf_st_other.ll ELF symbol table field st_other support, 2013-02-19 22:14:34 +00:00
elf-bigendian.ll
elf-gprel-32-64.ll
elf-N64.ll
elf-objdump.s
elf-reginfo.ll
elf-relsym.ll
elf-tls.ll
higher_highest.ll
hilo-addressing.s Mips specific standalone assembler addressing mode %hi and %lo. 2013-02-21 02:09:31 +00:00
lea_64.ll
lit.local.cfg
mips64-alu-instructions.s This patch that sets the EmitAlias flag in td files 2013-02-05 08:32:10 +00:00
mips64-register-names.s
mips64extins.ll
mips64shift.ll
mips_directives.s Mips specific standalone assembler addressing mode %hi and %lo. 2013-02-21 02:09:31 +00:00
mips_gprel16.ll
mips-alu-instructions.s This patch that sets the EmitAlias flag in td files 2013-02-05 08:32:10 +00:00
mips-coprocessor-encodings.s
mips-expansions.s
mips-fpu-instructions.s
mips-jump-instructions.s [mips] Add definition of JALR instruction which has two register operands. Change the 2013-02-07 19:48:00 +00:00
mips-memory-instructions.s
mips-register-names.s
mips-relocations.s
multi-64bit-func.ll
nabi-regs.s ELF symbol table field st_other support, 2013-02-20 23:11:17 +00:00
pr11877.s
r-mips-got-disp.ll
set-at-directive.s ELF symbol table field st_other support, 2013-02-20 23:11:17 +00:00
sext_64_32.ll
sym-offset.ll
xgot.ll