Sanjoy Das 477137f4d7 [LSR] Generate and use zero extends ... Summary: If a scale or a base register can be rewritten as "Zext({A,+,1})" then LSR will now consider a formula of that form in its normal cost computation. Depends on D9180 Reviewers: qcolombet, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9181 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243348 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-27 23:27:51 +00:00
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Analysis	Roll forward r243250	2015-07-26 19:10:03 +00:00
Assembler
Bindings
Bitcode
BugPoint	Fix typo in comment	2015-07-26 11:37:05 +00:00
CodeGen	WebAssembly: add a generic CPU	2015-07-27 23:25:54 +00:00
DebugInfo
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MC	Implemented encoding and intrinsics of the following instructions	2015-07-26 14:41:44 +00:00
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tools	[llvm-mc] Add --no-warn flag with -W alias to disable outputting warnings while assembling.	2015-07-27 22:39:14 +00:00
Transforms	[LSR] Generate and use zero extends	2015-07-27 23:27:51 +00:00
Unit
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lit.cfg
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