mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
182 lines
4.7 KiB
LLVM
182 lines
4.7 KiB
LLVM
; RUN: llc -march=arm64 < %s | FileCheck %s
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; rdar://10232252
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@object = external hidden global i64, section "__DATA, __objc_ivar", align 8
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; base + offset (imm9)
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; CHECK: @t1
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; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
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; CHECK: ret
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define void @t1() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 1
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + offset (> imm9)
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; CHECK: @t2
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; CHECK: sub [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #264
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; CHECK: ldr xzr, [
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; CHECK: [[ADDREG]]]
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; CHECK: ret
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define void @t2() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 -33
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
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; CHECK: @t3
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; CHECK: ldr xzr, [x{{[0-9]+}}, #32760]
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; CHECK: ret
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define void @t3() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4095
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + unsigned offset (> imm12 * size of type in bytes)
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; CHECK: @t4
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; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
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; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
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; CHECK: ret
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define void @t4() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4096
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + reg
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; CHECK: @t5
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; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3]
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; CHECK: ret
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define void @t5(i64 %a) {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 %a
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + reg + imm
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; CHECK: @t6
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; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3
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; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
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; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
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; CHECK: ret
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define void @t6(i64 %a) {
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%tmp1 = getelementptr inbounds i64, i64* @object, i64 %a
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%incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; Test base + wide immediate
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define void @t7(i64 %a) {
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; CHECK-LABEL: t7:
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; CHECK: orr w[[NUM:[0-9]+]], wzr, #0xffff
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; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
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%1 = add i64 %a, 65535 ;0xffff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t8(i64 %a) {
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; CHECK-LABEL: t8:
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; CHECK: movn [[REG:x[0-9]+]], #0x1235
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; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
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%1 = sub i64 %a, 4662 ;-4662 is 0xffffffffffffedca
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t9(i64 %a) {
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; CHECK-LABEL: t9:
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; CHECK: movn [[REG:x[0-9]+]], #0x1235, lsl #16
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; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
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%1 = add i64 -305463297, %a ;-305463297 is 0xffffffffedcaffff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t10(i64 %a) {
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; CHECK-LABEL: t10:
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; CHECK: movz [[REG:x[0-9]+]], #0x123, lsl #48
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; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
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%1 = add i64 %a, 81909218222800896 ;0x123000000000000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t11(i64 %a) {
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; CHECK-LABEL: t11:
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; CHECK: movz w[[NUM:[0-9]+]], #0x123, lsl #16
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; CHECK: movk w[[NUM:[0-9]+]], #0x4567
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; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
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%1 = add i64 %a, 19088743 ;0x1234567
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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; Test some boundaries that should not use movz/movn/orr
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define void @t12(i64 %a) {
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; CHECK-LABEL: t12:
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; CHECK: add [[REG:x[0-9]+]], x0, #4095
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, 4095 ;0xfff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t13(i64 %a) {
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; CHECK-LABEL: t13:
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; CHECK: sub [[REG:x[0-9]+]], x0, #4095
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, -4095 ;-0xfff
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t14(i64 %a) {
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; CHECK-LABEL: t14:
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; CHECK: add [[REG:x[0-9]+]], x0, #291, lsl #12
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, 1191936 ;0x123000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t15(i64 %a) {
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; CHECK-LABEL: t15:
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; CHECK: sub [[REG:x[0-9]+]], x0, #291, lsl #12
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; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
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%1 = add i64 %a, -1191936 ;0xFFFFFFFFFFEDD000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t16(i64 %a) {
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; CHECK-LABEL: t16:
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; CHECK: ldr xzr, [x0, #28672]
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%1 = add i64 %a, 28672 ;0x7000
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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define void @t17(i64 %a) {
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; CHECK-LABEL: t17:
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; CHECK: ldur xzr, [x0, #-256]
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%1 = add i64 %a, -256 ;-0x100
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%2 = inttoptr i64 %1 to i64*
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%3 = load volatile i64, i64* %2, align 8
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ret void
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}
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