llvm-6502/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

23 lines
687 B
LLVM

; RUN: llc -march=arm64 -o - %s | FileCheck %s
; ARM64ISelLowering.cpp was creating a new (floating-point) load for efficiency
; but not updating chain-successors of the old one. As a result, the two memory
; operations in this function both ended up direct successors to the EntryToken
; and could be reordered.
@var = global i32 0, align 4
define float @foo() {
; CHECK-LABEL: foo:
; Load must come before we clobber @var
; CHECK: adrp x[[VARBASE:[0-9]+]], {{_?var}}
; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]],
; CHECK: str wzr, [x[[VARBASE]],
%val = load i32, i32* @var, align 4
store i32 0, i32* @var, align 4
%fltval = sitofp i32 %val to float
ret float %fltval
}