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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
841 B
LLVM
35 lines
841 B
LLVM
; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
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; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V6
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; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
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; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V7
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; PR18364
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define i64 @f() #0 {
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entry:
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; V5-NOT: movw
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; V6-NOT: movw
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; V6T2: movw
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; V7: movw
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%y = alloca i64, align 8
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%z = alloca i64, align 8
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store i64 1, i64* %y, align 8
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store i64 11579764786944, i64* %z, align 8
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%0 = load i64, i64* %y, align 8
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%1 = load i64, i64* %z, align 8
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%sub = sub i64 %0, %1
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ret i64 %sub
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}
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define i64 @g(i64 %a, i32 %b) #0 {
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entry:
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; V5-NOT: movw
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; V6-NOT: movw
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; V6T2: movw
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; V7: movw
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%0 = mul i64 %a, 86400000
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%mul = add i64 %0, -210866803200000
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%conv = sext i32 %b to i64
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%add = add nsw i64 %mul, %conv
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ret i64 %add
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}
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