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1336daad86
llvm-6502/lib/Target/R600
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Michael Kuperstein 1336daad86 Use std::bitset for SubtargetFeatures 
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures. 
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237234 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 08:27:08 +00:00
..
AsmParser Use std::bitset for SubtargetFeatures 2015-05-13 08:27:08 +00:00
InstPrinter R600/SI: Initial support for assembler and inline assembly 2015-04-08 01:09:26 +00:00
MCTargetDesc Use std::bitset for SubtargetFeatures 2015-05-13 08:27:08 +00:00
TargetInfo
AMDGPU.h R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
AMDGPU.td R600: Fix comment that mentions AMDIL 2015-05-07 17:02:32 +00:00
AMDGPUAlwaysInlinePass.cpp R600: Fix always inline pass breaking noinline functions 2015-04-22 17:10:44 +00:00
AMDGPUAsmPrinter.cpp [AsmPrinter] Make AsmPrinter's OutStreamer member a unique_ptr. 2015-04-24 19:11:51 +00:00
AMDGPUAsmPrinter.h R600/SI: Add some missing overrides 2015-04-08 02:07:05 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
AMDGPUFrameLowering.h [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
AMDGPUInstrInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td R600/SI: Remove explicit m0 operand from v_interp instructions 2015-05-12 15:00:46 +00:00
AMDGPUInstructions.td R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
AMDGPUISelLowering.cpp R600/SI: Remove explicit m0 operand from v_interp instructions 2015-05-12 15:00:46 +00:00
AMDGPUISelLowering.h R600/SI: Remove explicit m0 operand from v_interp instructions 2015-05-12 15:00:46 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp R600/SI: Code cleanup 2015-05-04 16:45:08 +00:00
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp Remove superfluous .str() and replace std::string concatenation with Twine. 2015-03-27 17:51:30 +00:00
AMDGPURegisterInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
AMDGPURegisterInfo.h Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp R600/SI: Add assembler support for all CI and VI VOP1 instructions 2015-04-23 19:33:54 +00:00
AMDGPUSubtarget.h Reinstate revisions r234755, r234759, r234760 2015-04-30 17:15:56 +00:00
AMDGPUTargetMachine.cpp R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
AMDGPUTargetMachine.h Remove the target independent TargetMachine::getSubtarget and 2015-03-21 04:22:23 +00:00
AMDGPUTargetTransformInfo.cpp [X86] Disable loop unrolling in loop vectorization pass when VF is 1. 2015-05-06 17:12:25 +00:00
AMDGPUTargetTransformInfo.h [X86] Disable loop unrolling in loop vectorization pass when VF is 1. 2015-05-06 17:12:25 +00:00
AMDILCFGStructurizer.cpp CodeGen: Use the new DebugLoc API, NFC 2015-03-30 19:14:47 +00:00
AMDKernelCodeT.h
CaymanInstructions.td
CIInstructions.td R600/SI: Add assembler support for all CI and VI VOP1 instructions 2015-04-23 19:33:54 +00:00
CMakeLists.txt R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
EvergreenInstructions.td Reinstate revisions r234755, r234759, r234760 2015-04-30 17:15:56 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
R600InstrInfo.h
R600Instructions.td R600: Make FMIN/MAXNUM legal on all asics 2015-04-12 23:45:05 +00:00
R600Intrinsics.td
R600ISelLowering.cpp Reinstate revisions r234755, r234759, r234760 2015-04-30 17:15:56 +00:00
R600ISelLowering.h Reinstate revisions r234755, r234759, r234760 2015-04-30 17:15:56 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
R600Packetizer.cpp
R600RegisterInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
R600RegisterInfo.h Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp Reduce dyn_cast<> to isa<> or cast<> where possible. 2015-04-10 11:24:51 +00:00
R700Instructions.td
SIAnnotateControlFlow.cpp R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass 2015-05-01 03:44:08 +00:00
SIDefines.h R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIFixControlFlowLiveIntervals.cpp R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
SIFixSGPRCopies.cpp R600/SI: Remove M0Reg register class 2015-05-12 15:00:52 +00:00
SIFixSGPRLiveRanges.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
SIFoldOperands.cpp R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg) 2015-05-12 14:18:11 +00:00
SIInsertWaits.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
SIInstrFormats.td R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIInstrInfo.cpp R600/SI: Fix verifier error when producing v_madmk_f32 2015-04-24 01:57:58 +00:00
SIInstrInfo.h R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIInstrInfo.td R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
SIInstructions.td R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600/SI: Remove explicit m0 operand from v_interp instructions 2015-05-12 15:00:46 +00:00
SIISelLowering.h R600/SI: Remove explicit m0 operand from s_sendmsg 2015-05-12 14:18:14 +00:00
SILoadStoreOptimizer.cpp R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
SILowerControlFlow.cpp R600/SI: Fix indirect addressing with a negative constant offset 2015-04-23 20:32:01 +00:00
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIPrepareScratchRegs.cpp R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIRegisterInfo.cpp R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0 2015-05-12 15:00:53 +00:00
SIRegisterInfo.h Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
SIRegisterInfo.td R600/SI: Remove M0Reg register class 2015-05-12 15:00:52 +00:00
SISchedule.td
SIShrinkInstructions.cpp Purge unused includes throughout libSupport. 2015-03-23 18:07:13 +00:00
SITypeRewriter.cpp Remove more superfluous .str() and replace std::string concatenation with Twine. 2015-03-30 15:42:36 +00:00
VIInstrFormats.td
VIInstructions.td R600/SI: Add assembler support for all CI and VI VOP1 instructions 2015-04-23 19:33:54 +00:00