llvm-6502/test/MC/ELF/cfi-offset.s
Oliver Stannard bb804ee909 Emit DWARF3 call frame information when DWARF3+ debug info is requested
Currently, llvm always emits a DWARF CIE with a version of 1, even when emitting
DWARF 3 or 4, which both support CIE version 3. This patch makes it emit the
newer CIE version when we are emitting DWARF 3 or 4. This will not reduce
compatibility, as we already emit other DWARF3/4 features, and is worth doing as
the DWARF3 spec removed some ambiguities in the interpretation of call frame
information.

It also fixes a minor bug where the "return address" field of the CIE was
encoded as a ULEB128, which is only valid when the CIE version is 3. There are
no test changes for this, because (as far as I can tell) none of the platforms
that we test have a return address register with a DWARF register number >127.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211272 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-19 15:39:33 +00:00

48 lines
1.4 KiB
ArmAsm

// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s
f:
.cfi_startproc
nop
.cfi_offset %rbp, -16
nop
.cfi_endproc
// CHECK: Section {
// CHECK: Name: .eh_frame
// CHECK-NEXT: Type: SHT_PROGBITS
// CHECK-NEXT: Flags [
// CHECK-NEXT: SHF_ALLOC
// CHECK-NEXT: ]
// CHECK-NEXT: Address: 0x0
// CHECK-NEXT: Offset: 0x48
// CHECK-NEXT: Size: 48
// CHECK-NEXT: Link: 0
// CHECK-NEXT: Info: 0
// CHECK-NEXT: AddressAlignment: 8
// CHECK-NEXT: EntrySize: 0
// CHECK-NEXT: Relocations [
// CHECK-NEXT: ]
// CHECK-NEXT: SectionData (
// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001
// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000
// CHECK-NEXT: 0020: 00000000 02000000 00418602 00000000
// CHECK-NEXT: )
// CHECK-NEXT: }
// CHECK: Section {
// CHECK: Name: .rela.eh_frame
// CHECK-NEXT: Type: SHT_RELA
// CHECK-NEXT: Flags [
// CHECK-NEXT: ]
// CHECK-NEXT: Address: 0x0
// CHECK-NEXT: Offset: 0x390
// CHECK-NEXT: Size: 24
// CHECK-NEXT: Link: 7
// CHECK-NEXT: Info: 4
// CHECK-NEXT: AddressAlignment: 8
// CHECK-NEXT: EntrySize: 24
// CHECK-NEXT: Relocations [
// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0
// CHECK-NEXT: ]
// CHECK: }