llvm-6502/test/MC/X86/x86_errors.s
Kevin Enderby 84faf65912 Added a missing error check for X86 assembly with mismatched base and index
registers not both being 64-bit or both being 32-bit registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12 21:32:09 +00:00

31 lines
882 B
ArmAsm

// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
// RUN: FileCheck --check-prefix=64 < %t.err %s
// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
// RUN: FileCheck --check-prefix=32 < %t.err %s
// rdar://8204588
// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
cmp $0, 0(%eax)
// 32: error: register %rax is only available in 64-bit mode
addl $0, 0(%rax)
// 32: test.s:8:2: error: invalid instruction mnemonic 'movi'
# 8 "test.s"
movi $8,%eax
movl 0(%rax), 0(%edx) // error: invalid operand for instruction
// 32: error: instruction requires a CPU feature not currently enabled
sysexitq
// rdar://10710167
// 64: error: expected scale expression
lea (%rsp, %rbp, $4), %rax
// rdar://10423777
// 64: error: index register is 32-bit, but base register is 64-bit
movq (%rsi,%ecx),%xmm0