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07b59ba697
Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174610 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.4 KiB
C++
76 lines
2.4 KiB
C++
//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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using namespace llvm;
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AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
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const TargetInstrInfo &tii)
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: AMDGPUGenRegisterInfo(0),
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TM(tm),
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TII(tii)
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{ }
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
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const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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return &CalleeSavedReg;
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}
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void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(!"Subroutines not supported yet");
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}
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unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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assert(!"Subroutines not supported yet");
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return 0;
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}
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unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
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switch(IndirectIndex) {
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case 0: return AMDGPU::sub0;
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case 1: return AMDGPU::sub1;
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case 2: return AMDGPU::sub2;
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case 3: return AMDGPU::sub3;
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case 4: return AMDGPU::sub4;
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case 5: return AMDGPU::sub5;
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case 6: return AMDGPU::sub6;
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case 7: return AMDGPU::sub7;
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case 8: return AMDGPU::sub8;
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case 9: return AMDGPU::sub9;
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case 10: return AMDGPU::sub10;
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case 11: return AMDGPU::sub11;
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case 12: return AMDGPU::sub12;
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case 13: return AMDGPU::sub13;
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case 14: return AMDGPU::sub14;
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case 15: return AMDGPU::sub15;
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default: llvm_unreachable("indirect index out of range");
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}
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}
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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