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1. A delay slot filler that searches for valid instructions to fill the delay slot with. Previously NOPs would always be inserted into delay slots. 2. Support for MC based instruction printer added. 3. Support for MC based machine code generation and ELF file generation. ELF file generation does not yet completely work as much of the ELF support infrastructure is still x86/x86-64 specific. 4. General clean up of the MBlaze backend code. Much of the tablegen code has been cleanup and simplified. Bug Fixes: 1. Removed duplicate periods from subtarget feature descriptions. 2. Many of the instructions had bad machine code information in the tablegen files. Much of this has been fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
1.5 KiB
LLVM
67 lines
1.5 KiB
LLVM
; Ensure that floating point operations are lowered to function calls when the
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; FPU is not available in the hardware and that function calls are not used
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; when the FPU is available in the hardware.
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;
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; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
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; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
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define float @test_add(float %a, float %b) {
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; FUN: test_add:
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; FPU: test_add:
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%tmp.1 = fadd float %a, %b
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; FUN: brlid
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; FPU-NOT: brlid
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ret float %tmp.1
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; FUN: rtsd
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; FPU: rtsd
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; FUN-NOT: fadd
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; FPU-NEXT: fadd
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}
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define float @test_sub(float %a, float %b) {
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; FUN: test_sub:
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; FPU: test_sub:
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%tmp.1 = fsub float %a, %b
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; FUN: brlid
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; FPU-NOT: brlid
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ret float %tmp.1
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; FUN: rtsd
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; FPU: rtsd
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; FUN-NOT: frsub
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; FPU-NEXT: frsub
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}
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define float @test_mul(float %a, float %b) {
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; FUN: test_mul:
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; FPU: test_mul:
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%tmp.1 = fmul float %a, %b
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; FUN: brlid
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; FPU-NOT: brlid
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ret float %tmp.1
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; FUN: rtsd
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; FPU: rtsd
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; FUN-NOT: fmul
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; FPU-NEXT: fmul
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}
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define float @test_div(float %a, float %b) {
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; FUN: test_div:
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; FPU: test_div:
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%tmp.1 = fdiv float %a, %b
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; FUN: brlid
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; FPU-NOT: brlid
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ret float %tmp.1
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; FUN: rtsd
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; FPU: rtsd
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; FUN-NOT: fdiv
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; FPU-NEXT: fdiv
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}
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