Chad Rosier 13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar ... copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-12 19:13:08 +00:00
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AArch64	[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar	2013-11-12 19:13:08 +00:00
ARM	[ARM] Add support for MVFR2 which is new in ARMv8	2013-11-11 19:56:13 +00:00
Mips	Support for microMIPS trap instructions 1.	2013-11-07 14:35:24 +00:00
SystemZ	[SystemZ] Add comparisons of high words and memory	2013-10-01 15:00:44 +00:00
X86	Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.	2013-10-14 01:42:32 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00