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https://github.com/c64scene-ar/llvm-6502.git
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c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
1.6 KiB
LLVM
32 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone
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declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone
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; GCN-LABEL: {{^}}test_div_fixup_f32:
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; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
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; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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%result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fixup_f64:
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; GCN: v_div_fixup_f64
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define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind {
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%result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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