mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
1.4 KiB
LLVM
31 lines
1.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
|
|
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
|
|
|
|
declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone
|
|
|
|
; SI-LABEL: {{^}}test_trig_preop_f64:
|
|
; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]]
|
|
; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],
|
|
; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
|
|
; SI: buffer_store_dwordx2 [[RESULT]],
|
|
; SI: s_endpgm
|
|
define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
|
|
%a = load double, double addrspace(1)* %aptr, align 8
|
|
%b = load i32, i32 addrspace(1)* %bptr, align 4
|
|
%result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 %b) nounwind readnone
|
|
store double %result, double addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment:
|
|
; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],
|
|
; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
|
|
; SI: buffer_store_dwordx2 [[RESULT]],
|
|
; SI: s_endpgm
|
|
define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
|
|
%a = load double, double addrspace(1)* %aptr, align 8
|
|
%result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone
|
|
store double %result, double addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|