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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.8 KiB
LLVM
46 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
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;CHECK: DOT4 T{{[0-9]\.X}}
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;CHECK: MULADD_IEEE * T{{[0-9]\.W}}
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define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
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main_body:
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%0 = extractelement <4 x float> %reg1, i32 0
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%1 = extractelement <4 x float> %reg1, i32 1
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%2 = extractelement <4 x float> %reg1, i32 2
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%3 = extractelement <4 x float> %reg2, i32 0
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%4 = extractelement <4 x float> %reg2, i32 1
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%5 = extractelement <4 x float> %reg2, i32 2
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%6 = extractelement <4 x float> %reg3, i32 0
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%7 = extractelement <4 x float> %reg3, i32 1
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%8 = extractelement <4 x float> %reg3, i32 2
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%9 = load <4 x float>, <4 x float> addrspace(8)* null
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%10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
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%11 = call float @llvm.AMDGPU.dp4(<4 x float> %9, <4 x float> %9)
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%12 = fmul float %0, %3
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%13 = fadd float %12, %6
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%14 = fmul float %1, %4
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%15 = fadd float %14, %7
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%16 = fmul float %2, %5
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%17 = fadd float %16, %8
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%18 = fmul float %11, %11
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%19 = fadd float %18, %0
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%20 = insertelement <4 x float> undef, float %13, i32 0
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%21 = insertelement <4 x float> %20, float %15, i32 1
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%22 = insertelement <4 x float> %21, float %17, i32 2
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%23 = insertelement <4 x float> %22, float %19, i32 3
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%24 = call float @llvm.AMDGPU.dp4(<4 x float> %23, <4 x float> %10)
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%25 = insertelement <4 x float> undef, float %24, i32 0
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call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 2)
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ret void
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}
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; Function Attrs: readnone
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declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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attributes #0 = { "ShaderType"="1" }
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attributes #1 = { readnone }
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