llvm-6502/lib
Michael Liao 13d08bf415 Fix an issue of pseudo atomic instruction DAG schedule
- Add list of physical registers clobbered in pseudo atomic insts
  Physical registers are clobbered when pseudo atomic instructions are
  expanded. Add them in clobber list to prevent DAG scheduler to
  mis-schedule them after these insns are declared side-effect free.
- Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 21:47:38 +00:00
..
Analysis
Archive
AsmParser
Bitcode
CodeGen
DebugInfo
ExecutionEngine
IR More encapsulation work. 2013-01-22 21:15:51 +00:00
Linker
MC Add a warning when there is a macro defintion that has named parameters but 2013-01-22 21:44:53 +00:00
Object
Option
Support Initial patch for x32 ABI support. 2013-01-22 18:02:49 +00:00
TableGen
Target Fix an issue of pseudo atomic instruction DAG schedule 2013-01-22 21:47:38 +00:00
Transforms More encapsulation work. 2013-01-22 21:15:51 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile