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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
4.6 KiB
LLVM
132 lines
4.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.ceil.f32(float) nounwind readnone
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declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone
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declare <3 x float> @llvm.ceil.v3f32(<3 x float>) nounwind readnone
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declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
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declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone
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declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone
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; FUNC-LABEL: {{^}}fceil_f32:
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define void @fceil_f32(float addrspace(1)* %out, float %x) {
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%y = call float @llvm.ceil.f32(float %x) nounwind readnone
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store float %y, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v2f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) {
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%y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone
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store <2 x float> %y, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v3f32:
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; FIXME-SI: v_ceil_f32_e32
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; FIXME-SI: v_ceil_f32_e32
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; FIXME-SI: v_ceil_f32_e32
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; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) {
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%y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone
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store <3 x float> %y, <3 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v4f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) {
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%y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone
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store <4 x float> %y, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v8f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) {
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%y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone
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store <8 x float> %y, <8 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v16f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT4:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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define void @fceil_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) {
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%y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone
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store <16 x float> %y, <16 x float> addrspace(1)* %out
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ret void
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}
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