mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
7eeb607497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223603 91177308-0d34-0410-b5e6-96231b3b80d8
146 lines
3.1 KiB
TableGen
146 lines
3.1 KiB
TableGen
//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// VI Instruction format definitions.
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//
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//===----------------------------------------------------------------------===//
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class DSe_vi <bits<8> op> : Enc64 {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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bits<8> data0;
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bits<8> data1;
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bits<8> offset0;
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bits<8> offset1;
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let Inst{7-0} = offset0;
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let Inst{15-8} = offset1;
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let Inst{16} = gds;
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let Inst{24-17} = op;
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let Inst{31-26} = 0x36; //encoding
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let Inst{39-32} = addr;
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let Inst{47-40} = data0;
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let Inst{55-48} = data1;
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let Inst{63-56} = vdst;
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}
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class MUBUFe_vi <bits<7> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<1> lds;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{16} = lds;
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let Inst{17} = slc;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x38; //encoding
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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}
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class MTBUFe_vi <bits<4> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<4> dfmt;
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bits<3> nfmt;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{18-15} = op;
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let Inst{22-19} = dfmt;
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let Inst{25-23} = nfmt;
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let Inst{31-26} = 0x3a; //encoding
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{54} = slc;
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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}
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class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
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bits<7> sbase;
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bits<7> sdata;
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bits<1> glc;
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bits<20> offset;
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let Inst{5-0} = sbase{6-1};
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let Inst{12-6} = sdata;
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let Inst{16} = glc;
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let Inst{17} = imm;
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let Inst{25-18} = op;
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let Inst{31-26} = 0x30; //encoding
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let Inst{51-32} = offset;
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}
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class VOP3e_vi <bits<10> op> : Enc64 {
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bits<8> dst;
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<1> clamp;
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bits<2> omod;
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let Inst{7-0} = dst;
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let Inst{8} = src0_modifiers{1};
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let Inst{9} = src1_modifiers{1};
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let Inst{10} = src2_modifiers{1};
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let Inst{15} = clamp;
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let Inst{25-16} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{61} = src0_modifiers{0};
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let Inst{62} = src1_modifiers{0};
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let Inst{63} = src2_modifiers{0};
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}
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class EXPe_vi : EXPe {
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let Inst{31-26} = 0x31; //encoding
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}
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class VINTRPe_vi <bits<2> op> : VINTRPe <op> {
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let Inst{31-26} = 0x35; // encoding
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}
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