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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227293 91177308-0d34-0410-b5e6-96231b3b80d8
423 lines
14 KiB
C++
423 lines
14 KiB
C++
//=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass tries to make consecutive compares of values use same operands to
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// allow CSE pass to remove duplicated instructions. For this it analyzes
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// branches and adjusts comparisons with immediate values by converting:
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// * GE -> GT
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// * GT -> GE
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// * LT -> LE
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// * LE -> LT
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// and adjusting immediate values appropriately. It basically corrects two
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// immediate values towards each other to make them equal.
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//
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// Consider the following example in C:
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//
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// if ((a < 5 && ...) || (a > 5 && ...)) {
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// ~~~~~ ~~~~~
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// ^ ^
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// x y
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//
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// Here both "x" and "y" expressions compare "a" with "5". When "x" evaluates
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// to "false", "y" can just check flags set by the first comparison. As a
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// result of the canonicalization employed by
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// SelectionDAGBuilder::visitSwitchCase, DAGCombine, and other target-specific
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// code, assembly ends up in the form that is not CSE friendly:
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//
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// ...
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// cmp w8, #4
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// b.gt .LBB0_3
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// ...
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// .LBB0_3:
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// cmp w8, #6
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// b.lt .LBB0_6
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// ...
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//
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// Same assembly after the pass:
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//
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// ...
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// cmp w8, #5
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// b.ge .LBB0_3
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// ...
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// .LBB0_3:
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// cmp w8, #5 // <-- CSE pass removes this instruction
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// b.le .LBB0_6
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// ...
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//
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// Currently only SUBS and ADDS followed by b.?? are supported.
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//
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// TODO: maybe handle TBNZ/TBZ the same way as CMP when used instead for "a < 0"
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// TODO: handle other conditional instructions (e.g. CSET)
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// TODO: allow second branching to be anything if it doesn't require adjusting
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <cstdlib>
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#include <tuple>
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-condopt"
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STATISTIC(NumConditionsAdjusted, "Number of conditions adjusted");
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namespace {
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class AArch64ConditionOptimizer : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineDominatorTree *DomTree;
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public:
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// Stores immediate, compare instruction opcode and branch condition (in this
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// order) of adjusted comparison.
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typedef std::tuple<int, int, AArch64CC::CondCode> CmpInfo;
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static char ID;
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AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
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CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
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void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);
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bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
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int ToImm);
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "AArch64 Condition Optimizer";
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}
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};
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} // end anonymous namespace
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char AArch64ConditionOptimizer::ID = 0;
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namespace llvm {
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void initializeAArch64ConditionOptimizerPass(PassRegistry &);
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}
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INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt",
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"AArch64 CondOpt Pass", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt",
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"AArch64 CondOpt Pass", false, false)
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FunctionPass *llvm::createAArch64ConditionOptimizerPass() {
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return new AArch64ConditionOptimizer();
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}
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void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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// Finds compare instruction that corresponds to supported types of branching.
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// Returns the instruction or nullptr on failures or detecting unsupported
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// instructions.
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MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
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MachineBasicBlock *MBB) {
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MachineBasicBlock::iterator I = MBB->getFirstTerminator();
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if (I == MBB->end())
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return nullptr;
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if (I->getOpcode() != AArch64::Bcc)
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return nullptr;
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// Now find the instruction controlling the terminator.
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for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {
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--I;
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assert(!I->isTerminator() && "Spurious terminator");
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switch (I->getOpcode()) {
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// cmp is an alias for subs with a dead destination register.
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case AArch64::SUBSWri:
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case AArch64::SUBSXri:
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// cmn is an alias for adds with a dead destination register.
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case AArch64::ADDSWri:
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case AArch64::ADDSXri:
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if (I->getOperand(0).isDead())
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return I;
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DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n');
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return nullptr;
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// Prevent false positive case like:
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// cmp w19, #0
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// cinc w0, w19, gt
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// ...
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// fcmp d8, #0.0
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// b.gt .LBB0_5
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case AArch64::FCMPDri:
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case AArch64::FCMPSri:
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case AArch64::FCMPESri:
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case AArch64::FCMPEDri:
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case AArch64::SUBSWrr:
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case AArch64::SUBSXrr:
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case AArch64::ADDSWrr:
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case AArch64::ADDSXrr:
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case AArch64::FCMPSrr:
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case AArch64::FCMPDrr:
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case AArch64::FCMPESrr:
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case AArch64::FCMPEDrr:
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// Skip comparison instructions without immediate operands.
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return nullptr;
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}
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}
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DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
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return nullptr;
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}
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// Changes opcode adds <-> subs considering register operand width.
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static int getComplementOpc(int Opc) {
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switch (Opc) {
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case AArch64::ADDSWri: return AArch64::SUBSWri;
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case AArch64::ADDSXri: return AArch64::SUBSXri;
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case AArch64::SUBSWri: return AArch64::ADDSWri;
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case AArch64::SUBSXri: return AArch64::ADDSXri;
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default:
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llvm_unreachable("Unexpected opcode");
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}
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}
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// Changes form of comparison inclusive <-> exclusive.
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static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
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switch (Cmp) {
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case AArch64CC::GT: return AArch64CC::GE;
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case AArch64CC::GE: return AArch64CC::GT;
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case AArch64CC::LT: return AArch64CC::LE;
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case AArch64CC::LE: return AArch64CC::LT;
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default:
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llvm_unreachable("Unexpected condition code");
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}
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}
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// Transforms GT -> GE, GE -> GT, LT -> LE, LE -> LT by updating comparison
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// operator and condition code.
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AArch64ConditionOptimizer::CmpInfo AArch64ConditionOptimizer::adjustCmp(
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MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
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int Opc = CmpMI->getOpcode();
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// CMN (compare with negative immediate) is an alias to ADDS (as
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// "operand - negative" == "operand + positive")
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bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
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int Correction = (Cmp == AArch64CC::GT) ? 1 : -1;
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// Negate Correction value for comparison with negative immediate (CMN).
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if (Negative) {
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Correction = -Correction;
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}
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const int OldImm = (int)CmpMI->getOperand(2).getImm();
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const int NewImm = std::abs(OldImm + Correction);
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// Handle +0 -> -1 and -0 -> +1 (CMN with 0 immediate) transitions by
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// adjusting compare instruction opcode.
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if (OldImm == 0 && ((Negative && Correction == 1) ||
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(!Negative && Correction == -1))) {
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Opc = getComplementOpc(Opc);
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}
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return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
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}
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// Applies changes to comparison instruction suggested by adjustCmp().
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void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
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const CmpInfo &Info) {
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int Imm;
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int Opc;
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AArch64CC::CondCode Cmp;
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std::tie(Imm, Opc, Cmp) = Info;
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MachineBasicBlock *const MBB = CmpMI->getParent();
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// Change immediate in comparison instruction (ADDS or SUBS).
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BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
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.addOperand(CmpMI->getOperand(0))
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.addOperand(CmpMI->getOperand(1))
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.addImm(Imm)
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.addOperand(CmpMI->getOperand(3));
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CmpMI->eraseFromParent();
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// The fact that this comparison was picked ensures that it's related to the
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// first terminator instruction.
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MachineInstr *BrMI = MBB->getFirstTerminator();
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// Change condition in branch instruction.
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BuildMI(*MBB, BrMI, BrMI->getDebugLoc(), TII->get(AArch64::Bcc))
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.addImm(Cmp)
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.addOperand(BrMI->getOperand(1));
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BrMI->eraseFromParent();
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MBB->updateTerminator();
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++NumConditionsAdjusted;
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}
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// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
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// corresponding to TBB.
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// Returns true if parsing was successful, otherwise false is returned.
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static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
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// A normal br.cond simply has the condition code.
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if (Cond[0].getImm() != -1) {
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assert(Cond.size() == 1 && "Unknown Cond array format");
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CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
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return true;
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}
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return false;
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}
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// Adjusts one cmp instruction to another one if result of adjustment will allow
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// CSE. Returns true if compare instruction was changed, otherwise false is
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// returned.
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bool AArch64ConditionOptimizer::adjustTo(MachineInstr *CmpMI,
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AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm)
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{
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CmpInfo Info = adjustCmp(CmpMI, Cmp);
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if (std::get<0>(Info) == ToImm && std::get<1>(Info) == To->getOpcode()) {
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modifyCmp(CmpMI, Info);
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return true;
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}
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return false;
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}
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bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
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<< "********** Function: " << MF.getName() << '\n');
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TII = MF.getSubtarget().getInstrInfo();
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DomTree = &getAnalysis<MachineDominatorTree>();
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bool Changed = false;
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// Visit blocks in dominator tree pre-order. The pre-order enables multiple
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// cmp-conversions from the same head block.
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// Note that updateDomTree() modifies the children of the DomTree node
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// currently being visited. The df_iterator supports that; it doesn't look at
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// child_begin() / child_end() until after a node has been visited.
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for (MachineDomTreeNode *I : depth_first(DomTree)) {
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MachineBasicBlock *HBB = I->getBlock();
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SmallVector<MachineOperand, 4> HeadCond;
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MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
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if (TII->AnalyzeBranch(*HBB, TBB, FBB, HeadCond)) {
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continue;
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}
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// Equivalence check is to skip loops.
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if (!TBB || TBB == HBB) {
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continue;
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}
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SmallVector<MachineOperand, 4> TrueCond;
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MachineBasicBlock *TBB_TBB = nullptr, *TBB_FBB = nullptr;
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if (TII->AnalyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) {
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continue;
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}
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MachineInstr *HeadCmpMI = findSuitableCompare(HBB);
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if (!HeadCmpMI) {
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continue;
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}
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MachineInstr *TrueCmpMI = findSuitableCompare(TBB);
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if (!TrueCmpMI) {
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continue;
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}
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AArch64CC::CondCode HeadCmp;
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if (HeadCond.empty() || !parseCond(HeadCond, HeadCmp)) {
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continue;
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}
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AArch64CC::CondCode TrueCmp;
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if (TrueCond.empty() || !parseCond(TrueCond, TrueCmp)) {
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continue;
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}
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const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm();
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const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm();
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DEBUG(dbgs() << "Head branch:\n");
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DEBUG(dbgs() << "\tcondition: "
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<< AArch64CC::getCondCodeName(HeadCmp) << '\n');
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DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n');
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DEBUG(dbgs() << "True branch:\n");
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DEBUG(dbgs() << "\tcondition: "
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<< AArch64CC::getCondCodeName(TrueCmp) << '\n');
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DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n');
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if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::LT) ||
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(HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::GT)) &&
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std::abs(TrueImm - HeadImm) == 2) {
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// This branch transforms machine instructions that correspond to
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//
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// 1) (a > {TrueImm} && ...) || (a < {HeadImm} && ...)
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// 2) (a < {TrueImm} && ...) || (a > {HeadImm} && ...)
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//
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// into
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//
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// 1) (a >= {NewImm} && ...) || (a <= {NewImm} && ...)
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// 2) (a <= {NewImm} && ...) || (a >= {NewImm} && ...)
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CmpInfo HeadCmpInfo = adjustCmp(HeadCmpMI, HeadCmp);
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CmpInfo TrueCmpInfo = adjustCmp(TrueCmpMI, TrueCmp);
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if (std::get<0>(HeadCmpInfo) == std::get<0>(TrueCmpInfo) &&
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std::get<1>(HeadCmpInfo) == std::get<1>(TrueCmpInfo)) {
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modifyCmp(HeadCmpMI, HeadCmpInfo);
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modifyCmp(TrueCmpMI, TrueCmpInfo);
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Changed = true;
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}
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} else if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::GT) ||
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(HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::LT)) &&
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std::abs(TrueImm - HeadImm) == 1) {
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// This branch transforms machine instructions that correspond to
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//
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// 1) (a > {TrueImm} && ...) || (a > {HeadImm} && ...)
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// 2) (a < {TrueImm} && ...) || (a < {HeadImm} && ...)
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//
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// into
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//
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// 1) (a <= {NewImm} && ...) || (a > {NewImm} && ...)
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// 2) (a < {NewImm} && ...) || (a >= {NewImm} && ...)
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// GT -> GE transformation increases immediate value, so picking the
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// smaller one; LT -> LE decreases immediate value so invert the choice.
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bool adjustHeadCond = (HeadImm < TrueImm);
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if (HeadCmp == AArch64CC::LT) {
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adjustHeadCond = !adjustHeadCond;
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}
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if (adjustHeadCond) {
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Changed |= adjustTo(HeadCmpMI, HeadCmp, TrueCmpMI, TrueImm);
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} else {
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Changed |= adjustTo(TrueCmpMI, TrueCmp, HeadCmpMI, HeadImm);
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}
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}
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// Other transformation cases almost never occur due to generation of < or >
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// comparisons instead of <= and >=.
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}
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return Changed;
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}
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