Toma Tabacu f716ca43ca [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions. ... Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234401 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-08 12:15:05 +00:00
..
AArch64	AArch64: disallow "fmov sD, #-0.0" during assembly.	2015-04-07 22:49:47 +00:00
ARM	Write the section header in the end.	2015-04-08 11:41:24 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF
Disassembler	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
ELF	Write the section header in the end.	2015-04-08 11:41:24 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-04-03 01:46:11 +00:00
Markup
Mips	[mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions.	2015-04-08 12:15:05 +00:00
PowerPC	[PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions	2015-03-28 19:42:41 +00:00
R600	R600/SI: Initial support for assembler and inline assembly	2015-04-08 01:09:26 +00:00
Sparc
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	Fix the operand encoding in the test instruction.	2015-03-31 12:31:55 +00:00