mirror of
https://github.com/c64scene-ar/llvm-6502.git
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98a366d547
which better identifies what the optimization is doing. And is more flexible for future uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
1534 lines
53 KiB
C++
1534 lines
53 KiB
C++
//===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements bottom-up and top-down register pressure reduction list
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// schedulers, using standard algorithms. The basic approach uses a priority
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// queue of available nodes to schedule. One at a time, nodes are taken from
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// the priority queue (thus in priority order), checked for legality to
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// schedule, and emitted if legal.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "ScheduleDAGSDNodes.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/ADT/PriorityQueue.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <climits>
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using namespace llvm;
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STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
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STATISTIC(NumUnfolds, "Number of nodes unfolded");
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STATISTIC(NumDups, "Number of duplicated nodes");
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STATISTIC(NumPRCopies, "Number of physical register copies");
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static RegisterScheduler
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burrListDAGScheduler("list-burr",
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"Bottom-up register reduction list scheduling",
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createBURRListDAGScheduler);
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static RegisterScheduler
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tdrListrDAGScheduler("list-tdrr",
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"Top-down register reduction list scheduling",
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createTDRRListDAGScheduler);
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namespace {
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGRRList - The actual register reduction list scheduler
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/// implementation. This supports both top-down and bottom-up scheduling.
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///
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class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAGSDNodes {
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private:
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/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
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/// it is top-down.
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bool isBottomUp;
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/// AvailableQueue - The priority queue to use for the available SUnits.
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SchedulingPriorityQueue *AvailableQueue;
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/// LiveRegDefs - A set of physical registers and their definition
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/// that are "live". These nodes must be scheduled before any other nodes that
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/// modifies the registers can be scheduled.
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unsigned NumLiveRegs;
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std::vector<SUnit*> LiveRegDefs;
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std::vector<unsigned> LiveRegCycles;
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/// Topo - A topological ordering for SUnits which permits fast IsReachable
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/// and similar queries.
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ScheduleDAGTopologicalSort Topo;
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public:
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ScheduleDAGRRList(MachineFunction &mf,
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bool isbottomup,
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SchedulingPriorityQueue *availqueue)
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: ScheduleDAGSDNodes(mf), isBottomUp(isbottomup),
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AvailableQueue(availqueue), Topo(SUnits) {
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}
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~ScheduleDAGRRList() {
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delete AvailableQueue;
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}
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void Schedule();
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/// IsReachable - Checks if SU is reachable from TargetSU.
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bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
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return Topo.IsReachable(SU, TargetSU);
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}
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/// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
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/// create a cycle.
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bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
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return Topo.WillCreateCycle(SU, TargetSU);
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}
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/// AddPred - adds a predecessor edge to SUnit SU.
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/// This returns true if this is a new predecessor.
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/// Updates the topological ordering if required.
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void AddPred(SUnit *SU, const SDep &D) {
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Topo.AddPred(SU, D.getSUnit());
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SU->addPred(D);
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}
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/// RemovePred - removes a predecessor edge from SUnit SU.
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/// This returns true if an edge was removed.
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/// Updates the topological ordering if required.
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void RemovePred(SUnit *SU, const SDep &D) {
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Topo.RemovePred(SU, D.getSUnit());
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SU->removePred(D);
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}
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private:
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void ReleasePred(SUnit *SU, const SDep *PredEdge);
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void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
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void ReleaseSucc(SUnit *SU, const SDep *SuccEdge);
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void ReleaseSuccessors(SUnit *SU);
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void CapturePred(SDep *PredEdge);
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void ScheduleNodeBottomUp(SUnit*, unsigned);
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void ScheduleNodeTopDown(SUnit*, unsigned);
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void UnscheduleNodeBottomUp(SUnit*);
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void BacktrackBottomUp(SUnit*, unsigned, unsigned&);
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SUnit *CopyAndMoveSuccessors(SUnit*);
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void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
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const TargetRegisterClass*,
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const TargetRegisterClass*,
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SmallVector<SUnit*, 2>&);
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bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
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void ListScheduleTopDown();
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void ListScheduleBottomUp();
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/// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
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/// Updates the topological ordering if required.
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SUnit *CreateNewSUnit(SDNode *N) {
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unsigned NumSUnits = SUnits.size();
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SUnit *NewNode = NewSUnit(N);
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// Update the topological ordering.
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if (NewNode->NodeNum >= NumSUnits)
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Topo.InitDAGTopologicalSorting();
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return NewNode;
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}
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/// CreateClone - Creates a new SUnit from an existing one.
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/// Updates the topological ordering if required.
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SUnit *CreateClone(SUnit *N) {
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unsigned NumSUnits = SUnits.size();
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SUnit *NewNode = Clone(N);
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// Update the topological ordering.
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if (NewNode->NodeNum >= NumSUnits)
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Topo.InitDAGTopologicalSorting();
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return NewNode;
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}
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/// ForceUnitLatencies - Return true, since register-pressure-reducing
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/// scheduling doesn't need actual latency information.
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bool ForceUnitLatencies() const { return true; }
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGRRList::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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NumLiveRegs = 0;
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegCycles.resize(TRI->getNumRegs(), 0);
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// Build the scheduling graph.
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BuildSchedGraph();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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Topo.InitDAGTopologicalSorting();
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AvailableQueue->initNodes(SUnits);
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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if (isBottomUp)
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ListScheduleBottomUp();
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else
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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}
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//===----------------------------------------------------------------------===//
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
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SUnit *PredSU = PredEdge->getSUnit();
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--PredSU->NumSuccsLeft;
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft < 0) {
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cerr << "*** Scheduling failed! ***\n";
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PredSU->dump(this);
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cerr << " has been released too many times!\n";
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assert(0);
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}
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#endif
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// If all the node's successors are scheduled, this node is ready
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// to be scheduled. Ignore the special EntrySU node.
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
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PredSU->isAvailable = true;
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AvailableQueue->push(PredSU);
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}
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}
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void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU, unsigned CurCycle) {
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// Bottom up: release predecessors
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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ReleasePred(SU, &*I);
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if (I->isAssignedRegDep()) {
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// This is a physical register dependency and it's impossible or
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (!LiveRegDefs[I->getReg()]) {
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++NumLiveRegs;
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LiveRegDefs[I->getReg()] = I->getSUnit();
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LiveRegCycles[I->getReg()] = CurCycle;
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}
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}
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}
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}
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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DOUT << "*** Scheduling [" << CurCycle << "]: ";
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DEBUG(SU->dump(this));
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assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!");
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SU->setHeightToAtLeast(CurCycle);
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Sequence.push_back(SU);
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ReleasePredecessors(SU, CurCycle);
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// Release all the implicit physical register defs that are live.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isAssignedRegDep()) {
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if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
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assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
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assert(LiveRegDefs[I->getReg()] == SU &&
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"Physical register dependency violated?");
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--NumLiveRegs;
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LiveRegDefs[I->getReg()] = NULL;
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LiveRegCycles[I->getReg()] = 0;
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}
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}
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}
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SU->isScheduled = true;
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AvailableQueue->ScheduledNode(SU);
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}
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/// CapturePred - This does the opposite of ReleasePred. Since SU is being
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/// unscheduled, incrcease the succ left count of its predecessors. Remove
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/// them from AvailableQueue if necessary.
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void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
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SUnit *PredSU = PredEdge->getSUnit();
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if (PredSU->isAvailable) {
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PredSU->isAvailable = false;
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if (!PredSU->isPending)
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AvailableQueue->remove(PredSU);
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}
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++PredSU->NumSuccsLeft;
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}
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/// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
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/// its predecessor states to reflect the change.
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void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
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DOUT << "*** Unscheduling [" << SU->getHeight() << "]: ";
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DEBUG(SU->dump(this));
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AvailableQueue->UnscheduledNode(SU);
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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CapturePred(&*I);
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if (I->isAssignedRegDep() && SU->getHeight() == LiveRegCycles[I->getReg()]) {
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assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
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assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
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"Physical register dependency violated?");
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--NumLiveRegs;
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LiveRegDefs[I->getReg()] = NULL;
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LiveRegCycles[I->getReg()] = 0;
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}
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}
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isAssignedRegDep()) {
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if (!LiveRegDefs[I->getReg()]) {
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LiveRegDefs[I->getReg()] = SU;
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++NumLiveRegs;
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}
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if (I->getSUnit()->getHeight() < LiveRegCycles[I->getReg()])
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LiveRegCycles[I->getReg()] = I->getSUnit()->getHeight();
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}
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}
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SU->setHeightDirty();
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SU->isScheduled = false;
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SU->isAvailable = true;
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AvailableQueue->push(SU);
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}
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/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
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/// BTCycle in order to schedule a specific node.
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void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
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unsigned &CurCycle) {
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SUnit *OldSU = NULL;
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while (CurCycle > BtCycle) {
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OldSU = Sequence.back();
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Sequence.pop_back();
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if (SU->isSucc(OldSU))
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// Don't try to remove SU from AvailableQueue.
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SU->isAvailable = false;
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UnscheduleNodeBottomUp(OldSU);
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--CurCycle;
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}
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assert(!SU->isSucc(OldSU) && "Something is wrong!");
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++NumBacktracks;
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}
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/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
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/// successors to the newly created node.
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SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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if (SU->getNode()->getFlaggedNode())
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return NULL;
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SDNode *N = SU->getNode();
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if (!N)
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return NULL;
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SUnit *NewSU;
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bool TryUnfold = false;
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for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
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MVT VT = N->getValueType(i);
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if (VT == MVT::Flag)
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return NULL;
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else if (VT == MVT::Other)
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TryUnfold = true;
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}
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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const SDValue &Op = N->getOperand(i);
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MVT VT = Op.getNode()->getValueType(Op.getResNo());
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if (VT == MVT::Flag)
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return NULL;
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}
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if (TryUnfold) {
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SmallVector<SDNode*, 2> NewNodes;
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if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
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return NULL;
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DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
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assert(NewNodes.size() == 2 && "Expected a load folding node!");
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N = NewNodes[1];
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SDNode *LoadNode = NewNodes[0];
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unsigned NumVals = N->getNumValues();
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unsigned OldNumVals = SU->getNode()->getNumValues();
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for (unsigned i = 0; i != NumVals; ++i)
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DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
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DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
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SDValue(LoadNode, 1));
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// LoadNode may already exist. This can happen when there is another
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// load from the same location and producing the same type of value
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// but it has different alignment or volatileness.
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bool isNewLoad = true;
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SUnit *LoadSU;
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if (LoadNode->getNodeId() != -1) {
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LoadSU = &SUnits[LoadNode->getNodeId()];
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isNewLoad = false;
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} else {
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LoadSU = CreateNewSUnit(LoadNode);
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LoadNode->setNodeId(LoadSU->NodeNum);
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ComputeLatency(LoadSU);
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}
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SUnit *NewSU = CreateNewSUnit(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NewSU->NodeNum);
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const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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NewSU->isTwoAddress = true;
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break;
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}
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}
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if (TID.isCommutable())
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NewSU->isCommutable = true;
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ComputeLatency(NewSU);
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// Record all the edges to and from the old SU, by category.
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SmallVector<SDep, 4> ChainPreds;
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SmallVector<SDep, 4> ChainSuccs;
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SmallVector<SDep, 4> LoadPreds;
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SmallVector<SDep, 4> NodePreds;
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SmallVector<SDep, 4> NodeSuccs;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl())
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ChainPreds.push_back(*I);
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else if (I->getSUnit()->getNode() &&
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I->getSUnit()->getNode()->isOperandOf(LoadNode))
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LoadPreds.push_back(*I);
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else
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NodePreds.push_back(*I);
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}
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isCtrl())
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ChainSuccs.push_back(*I);
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else
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NodeSuccs.push_back(*I);
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}
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// Now assign edges to the newly-created nodes.
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for (unsigned i = 0, e = ChainPreds.size(); i != e; ++i) {
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const SDep &Pred = ChainPreds[i];
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RemovePred(SU, Pred);
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if (isNewLoad)
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AddPred(LoadSU, Pred);
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}
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for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
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const SDep &Pred = LoadPreds[i];
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RemovePred(SU, Pred);
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if (isNewLoad)
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AddPred(LoadSU, Pred);
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}
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for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
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const SDep &Pred = NodePreds[i];
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RemovePred(SU, Pred);
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AddPred(NewSU, Pred);
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}
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for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
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SDep D = NodeSuccs[i];
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SUnit *SuccDep = D.getSUnit();
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D.setSUnit(SU);
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RemovePred(SuccDep, D);
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D.setSUnit(NewSU);
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AddPred(SuccDep, D);
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}
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for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
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SDep D = ChainSuccs[i];
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SUnit *SuccDep = D.getSUnit();
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D.setSUnit(SU);
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RemovePred(SuccDep, D);
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if (isNewLoad) {
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D.setSUnit(LoadSU);
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AddPred(SuccDep, D);
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}
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}
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// Add a data dependency to reflect that NewSU reads the value defined
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// by LoadSU.
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AddPred(NewSU, SDep(LoadSU, SDep::Data, LoadSU->Latency));
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|
|
if (isNewLoad)
|
|
AvailableQueue->addNode(LoadSU);
|
|
AvailableQueue->addNode(NewSU);
|
|
|
|
++NumUnfolds;
|
|
|
|
if (NewSU->NumSuccsLeft == 0) {
|
|
NewSU->isAvailable = true;
|
|
return NewSU;
|
|
}
|
|
SU = NewSU;
|
|
}
|
|
|
|
DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
|
|
NewSU = CreateClone(SU);
|
|
|
|
// New SUnit has the exact same predecessors.
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I)
|
|
if (!I->isArtificial())
|
|
AddPred(NewSU, *I);
|
|
|
|
// Only copy scheduled successors. Cut them from old node's successor
|
|
// list and move them over.
|
|
SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->isArtificial())
|
|
continue;
|
|
SUnit *SuccSU = I->getSUnit();
|
|
if (SuccSU->isScheduled) {
|
|
SDep D = *I;
|
|
D.setSUnit(NewSU);
|
|
AddPred(SuccSU, D);
|
|
D.setSUnit(SU);
|
|
DelDeps.push_back(std::make_pair(SuccSU, D));
|
|
}
|
|
}
|
|
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
|
|
RemovePred(DelDeps[i].first, DelDeps[i].second);
|
|
|
|
AvailableQueue->updateNode(SU);
|
|
AvailableQueue->addNode(NewSU);
|
|
|
|
++NumDups;
|
|
return NewSU;
|
|
}
|
|
|
|
/// InsertCopiesAndMoveSuccs - Insert register copies and move all
|
|
/// scheduled successors of the given SUnit to the last copy.
|
|
void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
|
|
const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC,
|
|
SmallVector<SUnit*, 2> &Copies) {
|
|
SUnit *CopyFromSU = CreateNewSUnit(NULL);
|
|
CopyFromSU->CopySrcRC = SrcRC;
|
|
CopyFromSU->CopyDstRC = DestRC;
|
|
|
|
SUnit *CopyToSU = CreateNewSUnit(NULL);
|
|
CopyToSU->CopySrcRC = DestRC;
|
|
CopyToSU->CopyDstRC = SrcRC;
|
|
|
|
// Only copy scheduled successors. Cut them from old node's successor
|
|
// list and move them over.
|
|
SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->isArtificial())
|
|
continue;
|
|
SUnit *SuccSU = I->getSUnit();
|
|
if (SuccSU->isScheduled) {
|
|
SDep D = *I;
|
|
D.setSUnit(CopyToSU);
|
|
AddPred(SuccSU, D);
|
|
DelDeps.push_back(std::make_pair(SuccSU, *I));
|
|
}
|
|
}
|
|
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
|
|
RemovePred(DelDeps[i].first, DelDeps[i].second);
|
|
|
|
AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
|
|
AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0));
|
|
|
|
AvailableQueue->updateNode(SU);
|
|
AvailableQueue->addNode(CopyFromSU);
|
|
AvailableQueue->addNode(CopyToSU);
|
|
Copies.push_back(CopyFromSU);
|
|
Copies.push_back(CopyToSU);
|
|
|
|
++NumPRCopies;
|
|
}
|
|
|
|
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
|
|
/// definition of the specified node.
|
|
/// FIXME: Move to SelectionDAG?
|
|
static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
|
|
const TargetInstrInfo *TII) {
|
|
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
|
|
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
|
|
unsigned NumRes = TID.getNumDefs();
|
|
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
|
|
if (Reg == *ImpDef)
|
|
break;
|
|
++NumRes;
|
|
}
|
|
return N->getValueType(NumRes);
|
|
}
|
|
|
|
/// CheckForLiveRegDef - Return true and update live register vector if the
|
|
/// specified register def of the specified SUnit clobbers any "live" registers.
|
|
static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
|
|
std::vector<SUnit*> &LiveRegDefs,
|
|
SmallSet<unsigned, 4> &RegAdded,
|
|
SmallVector<unsigned, 4> &LRegs,
|
|
const TargetRegisterInfo *TRI) {
|
|
bool Added = false;
|
|
if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != SU) {
|
|
if (RegAdded.insert(Reg)) {
|
|
LRegs.push_back(Reg);
|
|
Added = true;
|
|
}
|
|
}
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
|
|
if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
|
|
if (RegAdded.insert(*Alias)) {
|
|
LRegs.push_back(*Alias);
|
|
Added = true;
|
|
}
|
|
}
|
|
return Added;
|
|
}
|
|
|
|
/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
|
|
/// scheduling of the given node to satisfy live physical register dependencies.
|
|
/// If the specific node is the last one that's available to schedule, do
|
|
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
|
|
bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
|
|
SmallVector<unsigned, 4> &LRegs){
|
|
if (NumLiveRegs == 0)
|
|
return false;
|
|
|
|
SmallSet<unsigned, 4> RegAdded;
|
|
// If this node would clobber any "live" register, then it's not ready.
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isAssignedRegDep())
|
|
CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
|
|
RegAdded, LRegs, TRI);
|
|
}
|
|
|
|
for (SDNode *Node = SU->getNode(); Node; Node = Node->getFlaggedNode()) {
|
|
if (Node->getOpcode() == ISD::INLINEASM) {
|
|
// Inline asm can clobber physical defs.
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
|
|
--NumOps; // Ignore the flag operand.
|
|
|
|
for (unsigned i = 2; i != NumOps;) {
|
|
unsigned Flags =
|
|
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
|
|
unsigned NumVals = (Flags & 0xffff) >> 3;
|
|
|
|
++i; // Skip the ID value.
|
|
if ((Flags & 7) == 2 || (Flags & 7) == 6) {
|
|
// Check for def of register or earlyclobber register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
|
|
}
|
|
} else
|
|
i += NumVals;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
if (!Node->isMachineOpcode())
|
|
continue;
|
|
const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
|
|
if (!TID.ImplicitDefs)
|
|
continue;
|
|
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg)
|
|
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
|
|
}
|
|
return !LRegs.empty();
|
|
}
|
|
|
|
|
|
/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
|
|
/// schedulers.
|
|
void ScheduleDAGRRList::ListScheduleBottomUp() {
|
|
unsigned CurCycle = 0;
|
|
|
|
// Release any predecessors of the special Exit node.
|
|
ReleasePredecessors(&ExitSU, CurCycle);
|
|
|
|
// Add root to Available queue.
|
|
if (!SUnits.empty()) {
|
|
SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
|
|
assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
|
|
RootSU->isAvailable = true;
|
|
AvailableQueue->push(RootSU);
|
|
}
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
// priority. If it is not ready put it back. Schedule the node.
|
|
SmallVector<SUnit*, 4> NotReady;
|
|
DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
|
|
Sequence.reserve(SUnits.size());
|
|
while (!AvailableQueue->empty()) {
|
|
bool Delayed = false;
|
|
LRegsMap.clear();
|
|
SUnit *CurSU = AvailableQueue->pop();
|
|
while (CurSU) {
|
|
SmallVector<unsigned, 4> LRegs;
|
|
if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
|
|
break;
|
|
Delayed = true;
|
|
LRegsMap.insert(std::make_pair(CurSU, LRegs));
|
|
|
|
CurSU->isPending = true; // This SU is not in AvailableQueue right now.
|
|
NotReady.push_back(CurSU);
|
|
CurSU = AvailableQueue->pop();
|
|
}
|
|
|
|
// All candidates are delayed due to live physical reg dependencies.
|
|
// Try backtracking, code duplication, or inserting cross class copies
|
|
// to resolve it.
|
|
if (Delayed && !CurSU) {
|
|
for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
|
|
SUnit *TrySU = NotReady[i];
|
|
SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
|
|
|
|
// Try unscheduling up to the point where it's safe to schedule
|
|
// this node.
|
|
unsigned LiveCycle = CurCycle;
|
|
for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
|
|
unsigned Reg = LRegs[j];
|
|
unsigned LCycle = LiveRegCycles[Reg];
|
|
LiveCycle = std::min(LiveCycle, LCycle);
|
|
}
|
|
SUnit *OldSU = Sequence[LiveCycle];
|
|
if (!WillCreateCycle(TrySU, OldSU)) {
|
|
BacktrackBottomUp(TrySU, LiveCycle, CurCycle);
|
|
// Force the current node to be scheduled before the node that
|
|
// requires the physical reg dep.
|
|
if (OldSU->isAvailable) {
|
|
OldSU->isAvailable = false;
|
|
AvailableQueue->remove(OldSU);
|
|
}
|
|
AddPred(TrySU, SDep(OldSU, SDep::Order, /*Latency=*/1,
|
|
/*Reg=*/0, /*isNormalMemory=*/false,
|
|
/*isMustAlias=*/false, /*isArtificial=*/true));
|
|
// If one or more successors has been unscheduled, then the current
|
|
// node is no longer avaialable. Schedule a successor that's now
|
|
// available instead.
|
|
if (!TrySU->isAvailable)
|
|
CurSU = AvailableQueue->pop();
|
|
else {
|
|
CurSU = TrySU;
|
|
TrySU->isPending = false;
|
|
NotReady.erase(NotReady.begin()+i);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!CurSU) {
|
|
// Can't backtrack. If it's too expensive to copy the value, then try
|
|
// duplicate the nodes that produces these "too expensive to copy"
|
|
// values to break the dependency. In case even that doesn't work,
|
|
// insert cross class copies.
|
|
// If it's not too expensive, i.e. cost != -1, issue copies.
|
|
SUnit *TrySU = NotReady[0];
|
|
SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
|
|
assert(LRegs.size() == 1 && "Can't handle this yet!");
|
|
unsigned Reg = LRegs[0];
|
|
SUnit *LRDef = LiveRegDefs[Reg];
|
|
MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
|
|
const TargetRegisterClass *RC =
|
|
TRI->getPhysicalRegisterRegClass(Reg, VT);
|
|
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
|
|
|
|
// If cross copy register class is null, then it must be possible copy
|
|
// the value directly. Do not try duplicate the def.
|
|
SUnit *NewDef = 0;
|
|
if (DestRC)
|
|
NewDef = CopyAndMoveSuccessors(LRDef);
|
|
else
|
|
DestRC = RC;
|
|
if (!NewDef) {
|
|
// Issue copies, these can be expensive cross register class copies.
|
|
SmallVector<SUnit*, 2> Copies;
|
|
InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
|
DOUT << "Adding an edge from SU #" << TrySU->NodeNum
|
|
<< " to SU #" << Copies.front()->NodeNum << "\n";
|
|
AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
|
|
/*Reg=*/0, /*isNormalMemory=*/false,
|
|
/*isMustAlias=*/false,
|
|
/*isArtificial=*/true));
|
|
NewDef = Copies.back();
|
|
}
|
|
|
|
DOUT << "Adding an edge from SU #" << NewDef->NodeNum
|
|
<< " to SU #" << TrySU->NodeNum << "\n";
|
|
LiveRegDefs[Reg] = NewDef;
|
|
AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
|
|
/*Reg=*/0, /*isNormalMemory=*/false,
|
|
/*isMustAlias=*/false,
|
|
/*isArtificial=*/true));
|
|
TrySU->isAvailable = false;
|
|
CurSU = NewDef;
|
|
}
|
|
|
|
assert(CurSU && "Unable to resolve live physical register dependencies!");
|
|
}
|
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
|
|
NotReady[i]->isPending = false;
|
|
// May no longer be available due to backtracking.
|
|
if (NotReady[i]->isAvailable)
|
|
AvailableQueue->push(NotReady[i]);
|
|
}
|
|
NotReady.clear();
|
|
|
|
if (CurSU)
|
|
ScheduleNodeBottomUp(CurSU, CurCycle);
|
|
++CurCycle;
|
|
}
|
|
|
|
// Reverse the order if it is bottom up.
|
|
std::reverse(Sequence.begin(), Sequence.end());
|
|
|
|
#ifndef NDEBUG
|
|
VerifySchedule(isBottomUp);
|
|
#endif
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-Down Scheduling
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
|
|
/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
|
|
void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
|
|
SUnit *SuccSU = SuccEdge->getSUnit();
|
|
--SuccSU->NumPredsLeft;
|
|
|
|
#ifndef NDEBUG
|
|
if (SuccSU->NumPredsLeft < 0) {
|
|
cerr << "*** Scheduling failed! ***\n";
|
|
SuccSU->dump(this);
|
|
cerr << " has been released too many times!\n";
|
|
assert(0);
|
|
}
|
|
#endif
|
|
|
|
// If all the node's predecessors are scheduled, this node is ready
|
|
// to be scheduled. Ignore the special ExitSU node.
|
|
if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
|
|
SuccSU->isAvailable = true;
|
|
AvailableQueue->push(SuccSU);
|
|
}
|
|
}
|
|
|
|
void ScheduleDAGRRList::ReleaseSuccessors(SUnit *SU) {
|
|
// Top down: release successors
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
assert(!I->isAssignedRegDep() &&
|
|
"The list-tdrr scheduler doesn't yet support physreg dependencies!");
|
|
|
|
ReleaseSucc(SU, &*I);
|
|
}
|
|
}
|
|
|
|
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
|
/// count of its successors. If a successor pending count is zero, add it to
|
|
/// the Available queue.
|
|
void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
|
DOUT << "*** Scheduling [" << CurCycle << "]: ";
|
|
DEBUG(SU->dump(this));
|
|
|
|
assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
|
|
SU->setDepthToAtLeast(CurCycle);
|
|
Sequence.push_back(SU);
|
|
|
|
ReleaseSuccessors(SU);
|
|
SU->isScheduled = true;
|
|
AvailableQueue->ScheduledNode(SU);
|
|
}
|
|
|
|
/// ListScheduleTopDown - The main loop of list scheduling for top-down
|
|
/// schedulers.
|
|
void ScheduleDAGRRList::ListScheduleTopDown() {
|
|
unsigned CurCycle = 0;
|
|
|
|
// Release any successors of the special Entry node.
|
|
ReleaseSuccessors(&EntrySU);
|
|
|
|
// All leaves to Available queue.
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
// It is available if it has no predecessors.
|
|
if (SUnits[i].Preds.empty()) {
|
|
AvailableQueue->push(&SUnits[i]);
|
|
SUnits[i].isAvailable = true;
|
|
}
|
|
}
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
// priority. If it is not ready put it back. Schedule the node.
|
|
Sequence.reserve(SUnits.size());
|
|
while (!AvailableQueue->empty()) {
|
|
SUnit *CurSU = AvailableQueue->pop();
|
|
|
|
if (CurSU)
|
|
ScheduleNodeTopDown(CurSU, CurCycle);
|
|
++CurCycle;
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
VerifySchedule(isBottomUp);
|
|
#endif
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// RegReductionPriorityQueue Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
|
|
// to reduce register pressure.
|
|
//
|
|
namespace {
|
|
template<class SF>
|
|
class RegReductionPriorityQueue;
|
|
|
|
/// Sorting functions for the Available queue.
|
|
struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
|
|
RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
|
|
bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
|
|
bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
|
|
|
|
bool operator()(const SUnit* left, const SUnit* right) const;
|
|
};
|
|
|
|
struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
|
|
RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
|
|
td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
|
|
td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
|
|
|
|
bool operator()(const SUnit* left, const SUnit* right) const;
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
/// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
|
|
/// Smaller number is the higher priority.
|
|
static unsigned
|
|
CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
|
|
unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
|
|
if (SethiUllmanNumber != 0)
|
|
return SethiUllmanNumber;
|
|
|
|
unsigned Extra = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl()) continue; // ignore chain preds
|
|
SUnit *PredSU = I->getSUnit();
|
|
unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
Extra = 0;
|
|
} else if (PredSethiUllman == SethiUllmanNumber)
|
|
++Extra;
|
|
}
|
|
|
|
SethiUllmanNumber += Extra;
|
|
|
|
if (SethiUllmanNumber == 0)
|
|
SethiUllmanNumber = 1;
|
|
|
|
return SethiUllmanNumber;
|
|
}
|
|
|
|
namespace {
|
|
template<class SF>
|
|
class VISIBILITY_HIDDEN RegReductionPriorityQueue
|
|
: public SchedulingPriorityQueue {
|
|
PriorityQueue<SUnit*, std::vector<SUnit*>, SF> Queue;
|
|
unsigned currentQueueId;
|
|
|
|
protected:
|
|
// SUnits - The SUnits for the current graph.
|
|
std::vector<SUnit> *SUnits;
|
|
|
|
const TargetInstrInfo *TII;
|
|
const TargetRegisterInfo *TRI;
|
|
ScheduleDAGRRList *scheduleDAG;
|
|
|
|
// SethiUllmanNumbers - The SethiUllman number for each node.
|
|
std::vector<unsigned> SethiUllmanNumbers;
|
|
|
|
public:
|
|
RegReductionPriorityQueue(const TargetInstrInfo *tii,
|
|
const TargetRegisterInfo *tri) :
|
|
Queue(SF(this)), currentQueueId(0),
|
|
TII(tii), TRI(tri), scheduleDAG(NULL) {}
|
|
|
|
void initNodes(std::vector<SUnit> &sunits) {
|
|
SUnits = &sunits;
|
|
// Add pseudo dependency edges for two-address nodes.
|
|
AddPseudoTwoAddrDeps();
|
|
// Reroute edges to nodes with multiple uses.
|
|
PrescheduleNodesWithMultipleUses();
|
|
// Calculate node priorities.
|
|
CalculateSethiUllmanNumbers();
|
|
}
|
|
|
|
void addNode(const SUnit *SU) {
|
|
unsigned SUSize = SethiUllmanNumbers.size();
|
|
if (SUnits->size() > SUSize)
|
|
SethiUllmanNumbers.resize(SUSize*2, 0);
|
|
CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
|
|
}
|
|
|
|
void updateNode(const SUnit *SU) {
|
|
SethiUllmanNumbers[SU->NodeNum] = 0;
|
|
CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
|
|
}
|
|
|
|
void releaseState() {
|
|
SUnits = 0;
|
|
SethiUllmanNumbers.clear();
|
|
}
|
|
|
|
unsigned getNodePriority(const SUnit *SU) const {
|
|
assert(SU->NodeNum < SethiUllmanNumbers.size());
|
|
unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
|
|
if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
|
// CopyToReg should be close to its uses to facilitate coalescing and
|
|
// avoid spilling.
|
|
return 0;
|
|
if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
|
|
Opc == TargetInstrInfo::SUBREG_TO_REG ||
|
|
Opc == TargetInstrInfo::INSERT_SUBREG)
|
|
// EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
|
|
// close to their uses to facilitate coalescing.
|
|
return 0;
|
|
if (SU->NumSuccs == 0 && SU->NumPreds != 0)
|
|
// If SU does not have a register use, i.e. it doesn't produce a value
|
|
// that would be consumed (e.g. store), then it terminates a chain of
|
|
// computation. Give it a large SethiUllman number so it will be
|
|
// scheduled right before its predecessors that it doesn't lengthen
|
|
// their live ranges.
|
|
return 0xffff;
|
|
if (SU->NumPreds == 0 && SU->NumSuccs != 0)
|
|
// If SU does not have a register def, schedule it close to its uses
|
|
// because it does not lengthen any live ranges.
|
|
return 0;
|
|
return SethiUllmanNumbers[SU->NodeNum];
|
|
}
|
|
|
|
unsigned size() const { return Queue.size(); }
|
|
|
|
bool empty() const { return Queue.empty(); }
|
|
|
|
void push(SUnit *U) {
|
|
assert(!U->NodeQueueId && "Node in the queue already");
|
|
U->NodeQueueId = ++currentQueueId;
|
|
Queue.push(U);
|
|
}
|
|
|
|
void push_all(const std::vector<SUnit *> &Nodes) {
|
|
for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
|
|
push(Nodes[i]);
|
|
}
|
|
|
|
SUnit *pop() {
|
|
if (empty()) return NULL;
|
|
SUnit *V = Queue.top();
|
|
Queue.pop();
|
|
V->NodeQueueId = 0;
|
|
return V;
|
|
}
|
|
|
|
void remove(SUnit *SU) {
|
|
assert(!Queue.empty() && "Queue is empty!");
|
|
assert(SU->NodeQueueId != 0 && "Not in queue!");
|
|
Queue.erase_one(SU);
|
|
SU->NodeQueueId = 0;
|
|
}
|
|
|
|
void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
|
|
scheduleDAG = scheduleDag;
|
|
}
|
|
|
|
protected:
|
|
bool canClobber(const SUnit *SU, const SUnit *Op);
|
|
void AddPseudoTwoAddrDeps();
|
|
void PrescheduleNodesWithMultipleUses();
|
|
void CalculateSethiUllmanNumbers();
|
|
};
|
|
|
|
typedef RegReductionPriorityQueue<bu_ls_rr_sort>
|
|
BURegReductionPriorityQueue;
|
|
|
|
typedef RegReductionPriorityQueue<td_ls_rr_sort>
|
|
TDRegReductionPriorityQueue;
|
|
}
|
|
|
|
/// closestSucc - Returns the scheduled cycle of the successor which is
|
|
/// closest to the current cycle.
|
|
static unsigned closestSucc(const SUnit *SU) {
|
|
unsigned MaxHeight = 0;
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl()) continue; // ignore chain succs
|
|
unsigned Height = I->getSUnit()->getHeight();
|
|
// If there are bunch of CopyToRegs stacked up, they should be considered
|
|
// to be at the same position.
|
|
if (I->getSUnit()->getNode() &&
|
|
I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
|
|
Height = closestSucc(I->getSUnit())+1;
|
|
if (Height > MaxHeight)
|
|
MaxHeight = Height;
|
|
}
|
|
return MaxHeight;
|
|
}
|
|
|
|
/// calcMaxScratches - Returns an cost estimate of the worse case requirement
|
|
/// for scratch registers, i.e. number of data dependencies.
|
|
static unsigned calcMaxScratches(const SUnit *SU) {
|
|
unsigned Scratches = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl()) continue; // ignore chain preds
|
|
Scratches++;
|
|
}
|
|
return Scratches;
|
|
}
|
|
|
|
// Bottom up
|
|
bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
|
unsigned LPriority = SPQ->getNodePriority(left);
|
|
unsigned RPriority = SPQ->getNodePriority(right);
|
|
if (LPriority != RPriority)
|
|
return LPriority > RPriority;
|
|
|
|
// Try schedule def + use closer when Sethi-Ullman numbers are the same.
|
|
// e.g.
|
|
// t1 = op t2, c1
|
|
// t3 = op t4, c2
|
|
//
|
|
// and the following instructions are both ready.
|
|
// t2 = op c3
|
|
// t4 = op c4
|
|
//
|
|
// Then schedule t2 = op first.
|
|
// i.e.
|
|
// t4 = op c4
|
|
// t2 = op c3
|
|
// t1 = op t2, c1
|
|
// t3 = op t4, c2
|
|
//
|
|
// This creates more short live intervals.
|
|
unsigned LDist = closestSucc(left);
|
|
unsigned RDist = closestSucc(right);
|
|
if (LDist != RDist)
|
|
return LDist < RDist;
|
|
|
|
// How many registers becomes live when the node is scheduled.
|
|
unsigned LScratch = calcMaxScratches(left);
|
|
unsigned RScratch = calcMaxScratches(right);
|
|
if (LScratch != RScratch)
|
|
return LScratch > RScratch;
|
|
|
|
if (left->getHeight() != right->getHeight())
|
|
return left->getHeight() > right->getHeight();
|
|
|
|
if (left->getDepth() != right->getDepth())
|
|
return left->getDepth() < right->getDepth();
|
|
|
|
assert(left->NodeQueueId && right->NodeQueueId &&
|
|
"NodeQueueId cannot be zero");
|
|
return (left->NodeQueueId > right->NodeQueueId);
|
|
}
|
|
|
|
template<class SF>
|
|
bool
|
|
RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) {
|
|
if (SU->isTwoAddress) {
|
|
unsigned Opc = SU->getNode()->getMachineOpcode();
|
|
const TargetInstrDesc &TID = TII->get(Opc);
|
|
unsigned NumRes = TID.getNumDefs();
|
|
unsigned NumOps = TID.getNumOperands() - NumRes;
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
|
if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
|
|
SDNode *DU = SU->getNode()->getOperand(i).getNode();
|
|
if (DU->getNodeId() != -1 &&
|
|
Op->OrigNode == &(*SUnits)[DU->getNodeId()])
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
/// hasCopyToRegUse - Return true if SU has a value successor that is a
|
|
/// CopyToReg node.
|
|
static bool hasCopyToRegUse(const SUnit *SU) {
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl()) continue;
|
|
const SUnit *SuccSU = I->getSUnit();
|
|
if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg)
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
|
|
/// physical register defs.
|
|
static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
|
|
const TargetInstrInfo *TII,
|
|
const TargetRegisterInfo *TRI) {
|
|
SDNode *N = SuccSU->getNode();
|
|
unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
|
|
const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
|
|
assert(ImpDefs && "Caller should check hasPhysRegDefs");
|
|
for (const SDNode *SUNode = SU->getNode(); SUNode;
|
|
SUNode = SUNode->getFlaggedNode()) {
|
|
if (!SUNode->isMachineOpcode())
|
|
continue;
|
|
const unsigned *SUImpDefs =
|
|
TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
|
|
if (!SUImpDefs)
|
|
return false;
|
|
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
|
|
MVT VT = N->getValueType(i);
|
|
if (VT == MVT::Flag || VT == MVT::Other)
|
|
continue;
|
|
if (!N->hasAnyUseOfValue(i))
|
|
continue;
|
|
unsigned Reg = ImpDefs[i - NumDefs];
|
|
for (;*SUImpDefs; ++SUImpDefs) {
|
|
unsigned SUReg = *SUImpDefs;
|
|
if (TRI->regsOverlap(Reg, SUReg))
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// PrescheduleNodesWithMultipleUses - Nodes with multiple uses
|
|
/// are not handled well by the general register pressure reduction
|
|
/// heuristics. When presented with code like this:
|
|
///
|
|
/// N
|
|
/// / |
|
|
/// / |
|
|
/// U store
|
|
/// |
|
|
/// ...
|
|
///
|
|
/// the heuristics tend to push the store up, but since the
|
|
/// operand of the store has another use (U), this would increase
|
|
/// the length of that other use (the U->N edge).
|
|
///
|
|
/// This function transforms code like the above to route U's
|
|
/// dependence through the store when possible, like this:
|
|
///
|
|
/// N
|
|
/// ||
|
|
/// ||
|
|
/// store
|
|
/// |
|
|
/// U
|
|
/// |
|
|
/// ...
|
|
///
|
|
/// This results in the store being scheduled immediately
|
|
/// after N, which shortens the U->N live range, reducing
|
|
/// register pressure.
|
|
///
|
|
template<class SF>
|
|
void RegReductionPriorityQueue<SF>::PrescheduleNodesWithMultipleUses() {
|
|
// Visit all the nodes in topological order, working top-down.
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
|
|
SUnit *SU = &(*SUnits)[i];
|
|
// For now, only look at nodes with no data successors, such as stores.
|
|
// These are especially important, due to the heuristics in
|
|
// getNodePriority for nodes with no data successors.
|
|
if (SU->NumSuccs != 0)
|
|
continue;
|
|
// For now, only look at nodes with exactly one data predecessor.
|
|
if (SU->NumPreds != 1)
|
|
continue;
|
|
// Avoid prescheduling copies to virtual registers, which don't behave
|
|
// like other nodes from the perspective of scheduling heuristics.
|
|
if (SDNode *N = SU->getNode())
|
|
if (N->getOpcode() == ISD::CopyToReg &&
|
|
TargetRegisterInfo::isVirtualRegister
|
|
(cast<RegisterSDNode>(N->getOperand(1))->getReg()))
|
|
continue;
|
|
|
|
// Locate the single data predecessor.
|
|
SUnit *PredSU = 0;
|
|
for (SUnit::const_pred_iterator II = SU->Preds.begin(),
|
|
EE = SU->Preds.end(); II != EE; ++II)
|
|
if (!II->isCtrl()) {
|
|
PredSU = II->getSUnit();
|
|
break;
|
|
}
|
|
assert(PredSU);
|
|
|
|
// Don't rewrite edges that carry physregs, because that requires additional
|
|
// support infrastructure.
|
|
if (PredSU->hasPhysRegDefs)
|
|
continue;
|
|
// Short-circuit the case where SU is PredSU's only data successor.
|
|
if (PredSU->NumSuccs == 1)
|
|
continue;
|
|
// Avoid prescheduling to copies from virtual registers, which don't behave
|
|
// like other nodes from the perspective of scheduling // heuristics.
|
|
if (SDNode *N = SU->getNode())
|
|
if (N->getOpcode() == ISD::CopyFromReg &&
|
|
TargetRegisterInfo::isVirtualRegister
|
|
(cast<RegisterSDNode>(N->getOperand(1))->getReg()))
|
|
continue;
|
|
|
|
// Perform checks on the successors of PredSU.
|
|
for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),
|
|
EE = PredSU->Succs.end(); II != EE; ++II) {
|
|
SUnit *PredSuccSU = II->getSUnit();
|
|
if (PredSuccSU == SU) continue;
|
|
// If PredSU has another successor with no data successors, for
|
|
// now don't attempt to choose either over the other.
|
|
if (PredSuccSU->NumSuccs == 0)
|
|
goto outer_loop_continue;
|
|
// Don't break physical register dependencies.
|
|
if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
|
|
if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
|
|
goto outer_loop_continue;
|
|
// Don't introduce graph cycles.
|
|
if (scheduleDAG->IsReachable(SU, PredSuccSU))
|
|
goto outer_loop_continue;
|
|
}
|
|
|
|
// Ok, the transformation is safe and the heuristics suggest it is
|
|
// profitable. Update the graph.
|
|
DOUT << "Prescheduling SU # " << SU->NodeNum
|
|
<< " next to PredSU # " << PredSU->NodeNum
|
|
<< " to guide scheduling in the presence of multiple uses\n";
|
|
for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
|
|
SDep Edge = PredSU->Succs[i];
|
|
assert(!Edge.isAssignedRegDep());
|
|
SUnit *SuccSU = Edge.getSUnit();
|
|
if (SuccSU != SU) {
|
|
Edge.setSUnit(PredSU);
|
|
scheduleDAG->RemovePred(SuccSU, Edge);
|
|
scheduleDAG->AddPred(SU, Edge);
|
|
Edge.setSUnit(SU);
|
|
scheduleDAG->AddPred(SuccSU, Edge);
|
|
--i;
|
|
}
|
|
}
|
|
outer_loop_continue:;
|
|
}
|
|
}
|
|
|
|
/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
|
|
/// it as a def&use operand. Add a pseudo control edge from it to the other
|
|
/// node (if it won't create a cycle) so the two-address one will be scheduled
|
|
/// first (lower in the schedule). If both nodes are two-address, favor the
|
|
/// one that has a CopyToReg use (more likely to be a loop induction update).
|
|
/// If both are two-address, but one is commutable while the other is not
|
|
/// commutable, favor the one that's not commutable.
|
|
template<class SF>
|
|
void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
|
|
SUnit *SU = &(*SUnits)[i];
|
|
if (!SU->isTwoAddress)
|
|
continue;
|
|
|
|
SDNode *Node = SU->getNode();
|
|
if (!Node || !Node->isMachineOpcode() || SU->getNode()->getFlaggedNode())
|
|
continue;
|
|
|
|
unsigned Opc = Node->getMachineOpcode();
|
|
const TargetInstrDesc &TID = TII->get(Opc);
|
|
unsigned NumRes = TID.getNumDefs();
|
|
unsigned NumOps = TID.getNumOperands() - NumRes;
|
|
for (unsigned j = 0; j != NumOps; ++j) {
|
|
if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
|
|
continue;
|
|
SDNode *DU = SU->getNode()->getOperand(j).getNode();
|
|
if (DU->getNodeId() == -1)
|
|
continue;
|
|
const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
|
|
if (!DUSU) continue;
|
|
for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
|
|
E = DUSU->Succs.end(); I != E; ++I) {
|
|
if (I->isCtrl()) continue;
|
|
SUnit *SuccSU = I->getSUnit();
|
|
if (SuccSU == SU)
|
|
continue;
|
|
// Be conservative. Ignore if nodes aren't at roughly the same
|
|
// depth and height.
|
|
if (SuccSU->getHeight() < SU->getHeight() &&
|
|
(SU->getHeight() - SuccSU->getHeight()) > 1)
|
|
continue;
|
|
// Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge
|
|
// constrains whatever is using the copy, instead of the copy
|
|
// itself. In the case that the copy is coalesced, this
|
|
// preserves the intent of the pseudo two-address heurietics.
|
|
while (SuccSU->Succs.size() == 1 &&
|
|
SuccSU->getNode()->isMachineOpcode() &&
|
|
SuccSU->getNode()->getMachineOpcode() ==
|
|
TargetInstrInfo::COPY_TO_REGCLASS)
|
|
SuccSU = SuccSU->Succs.front().getSUnit();
|
|
// Don't constrain non-instruction nodes.
|
|
if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
|
|
continue;
|
|
// Don't constrain nodes with physical register defs if the
|
|
// predecessor can clobber them.
|
|
if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
|
|
if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
|
|
continue;
|
|
}
|
|
// Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
|
|
// these may be coalesced away. We want them close to their uses.
|
|
unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
|
|
if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
|
|
SuccOpc == TargetInstrInfo::INSERT_SUBREG ||
|
|
SuccOpc == TargetInstrInfo::SUBREG_TO_REG)
|
|
continue;
|
|
if ((!canClobber(SuccSU, DUSU) ||
|
|
(hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
|
|
(!SU->isCommutable && SuccSU->isCommutable)) &&
|
|
!scheduleDAG->IsReachable(SuccSU, SU)) {
|
|
DOUT << "Adding a pseudo-two-addr edge from SU # " << SU->NodeNum
|
|
<< " to SU #" << SuccSU->NodeNum << "\n";
|
|
scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
|
|
/*Reg=*/0, /*isNormalMemory=*/false,
|
|
/*isMustAlias=*/false,
|
|
/*isArtificial=*/true));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
|
|
/// scheduling units.
|
|
template<class SF>
|
|
void RegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
|
CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
|
|
}
|
|
|
|
/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
|
|
/// predecessors of the successors of the SUnit SU. Stop when the provided
|
|
/// limit is exceeded.
|
|
static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
|
|
unsigned Limit) {
|
|
unsigned Sum = 0;
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
const SUnit *SuccSU = I->getSUnit();
|
|
for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
|
|
EE = SuccSU->Preds.end(); II != EE; ++II) {
|
|
SUnit *PredSU = II->getSUnit();
|
|
if (!PredSU->isScheduled)
|
|
if (++Sum > Limit)
|
|
return Sum;
|
|
}
|
|
}
|
|
return Sum;
|
|
}
|
|
|
|
|
|
// Top down
|
|
bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
|
unsigned LPriority = SPQ->getNodePriority(left);
|
|
unsigned RPriority = SPQ->getNodePriority(right);
|
|
bool LIsTarget = left->getNode() && left->getNode()->isMachineOpcode();
|
|
bool RIsTarget = right->getNode() && right->getNode()->isMachineOpcode();
|
|
bool LIsFloater = LIsTarget && left->NumPreds == 0;
|
|
bool RIsFloater = RIsTarget && right->NumPreds == 0;
|
|
unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
|
|
unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0;
|
|
|
|
if (left->NumSuccs == 0 && right->NumSuccs != 0)
|
|
return false;
|
|
else if (left->NumSuccs != 0 && right->NumSuccs == 0)
|
|
return true;
|
|
|
|
if (LIsFloater)
|
|
LBonus -= 2;
|
|
if (RIsFloater)
|
|
RBonus -= 2;
|
|
if (left->NumSuccs == 1)
|
|
LBonus += 2;
|
|
if (right->NumSuccs == 1)
|
|
RBonus += 2;
|
|
|
|
if (LPriority+LBonus != RPriority+RBonus)
|
|
return LPriority+LBonus < RPriority+RBonus;
|
|
|
|
if (left->getDepth() != right->getDepth())
|
|
return left->getDepth() < right->getDepth();
|
|
|
|
if (left->NumSuccsLeft != right->NumSuccsLeft)
|
|
return left->NumSuccsLeft > right->NumSuccsLeft;
|
|
|
|
assert(left->NodeQueueId && right->NodeQueueId &&
|
|
"NodeQueueId cannot be zero");
|
|
return (left->NodeQueueId > right->NodeQueueId);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
llvm::ScheduleDAGSDNodes *
|
|
llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
|
|
const TargetMachine &TM = IS->TM;
|
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
|
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
|
|
|
|
BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
|
|
|
|
ScheduleDAGRRList *SD =
|
|
new ScheduleDAGRRList(*IS->MF, true, PQ);
|
|
PQ->setScheduleDAG(SD);
|
|
return SD;
|
|
}
|
|
|
|
llvm::ScheduleDAGSDNodes *
|
|
llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
|
|
const TargetMachine &TM = IS->TM;
|
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
|
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
|
|
|
|
TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI);
|
|
|
|
ScheduleDAGRRList *SD =
|
|
new ScheduleDAGRRList(*IS->MF, false, PQ);
|
|
PQ->setScheduleDAG(SD);
|
|
return SD;
|
|
}
|