mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Patch by Kai! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167085 91177308-0d34-0410-b5e6-96231b3b80d8
696 lines
25 KiB
C++
696 lines
25 KiB
C++
//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineOperand class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
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#define LLVM_CODEGEN_MACHINEOPERAND_H
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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namespace llvm {
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class BlockAddress;
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class ConstantFP;
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class ConstantInt;
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class GlobalValue;
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class MachineBasicBlock;
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class MachineInstr;
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class MachineRegisterInfo;
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class MDNode;
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class TargetMachine;
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class TargetRegisterInfo;
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class hash_code;
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class raw_ostream;
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class MCSymbol;
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/// MachineOperand class - Representation of each machine instruction operand.
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///
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class MachineOperand {
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public:
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enum MachineOperandType {
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MO_Register, ///< Register operand.
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MO_Immediate, ///< Immediate operand
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MO_CImmediate, ///< Immediate >64bit operand
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MO_FPImmediate, ///< Floating-point immediate operand
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MO_MachineBasicBlock, ///< MachineBasicBlock reference
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MO_FrameIndex, ///< Abstract Stack Frame Index
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MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
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MO_TargetIndex, ///< Target-dependent index+offset operand.
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MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
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MO_ExternalSymbol, ///< Name of external global symbol
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MO_GlobalAddress, ///< Address of a global value
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MO_BlockAddress, ///< Address of a basic block
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MO_RegisterMask, ///< Mask of preserved registers.
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MO_Metadata, ///< Metadata reference (for debug info)
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MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
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};
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private:
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/// OpKind - Specify what kind of operand this is. This discriminates the
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/// union.
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unsigned char OpKind; // MachineOperandType
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// This union is discriminated by OpKind.
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union {
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/// SubReg - Subregister number, only valid for MO_Register. A value of 0
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/// indicates the MO_Register has no subReg.
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unsigned char SubReg;
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/// TargetFlags - This is a set of target-specific operand flags.
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unsigned char TargetFlags;
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};
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/// TiedTo - Non-zero when this register operand is tied to another register
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/// operand. The encoding of this field is described in the block comment
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/// before MachineInstr::tieOperands().
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unsigned char TiedTo : 4;
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/// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
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/// operands.
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/// IsDef - True if this is a def, false if this is a use of the register.
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///
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bool IsDef : 1;
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/// IsImp - True if this is an implicit def or use, false if it is explicit.
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///
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bool IsImp : 1;
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/// IsKill - True if this instruction is the last use of the register on this
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/// path through the function. This is only valid on uses of registers.
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bool IsKill : 1;
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/// IsDead - True if this register is never used by a subsequent instruction.
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/// This is only valid on definitions of registers.
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bool IsDead : 1;
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/// IsUndef - True if this register operand reads an "undef" value, i.e. the
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/// read value doesn't matter. This flag can be set on both use and def
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/// operands. On a sub-register def operand, it refers to the part of the
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/// register that isn't written. On a full-register def operand, it is a
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/// noop. See readsReg().
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///
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/// This is only valid on registers.
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///
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/// Note that an instruction may have multiple <undef> operands referring to
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/// the same register. In that case, the instruction may depend on those
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/// operands reading the same dont-care value. For example:
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///
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/// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
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///
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/// Any register can be used for %vreg2, and its value doesn't matter, but
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/// the two operands must be the same register.
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///
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bool IsUndef : 1;
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/// IsInternalRead - True if this operand reads a value that was defined
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/// inside the same instruction or bundle. This flag can be set on both use
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/// and def operands. On a sub-register def operand, it refers to the part
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/// of the register that isn't written. On a full-register def operand, it
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/// is a noop.
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///
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/// When this flag is set, the instruction bundle must contain at least one
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/// other def of the register. If multiple instructions in the bundle define
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/// the register, the meaning is target-defined.
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bool IsInternalRead : 1;
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/// IsEarlyClobber - True if this MO_Register 'def' operand is written to
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/// by the MachineInstr before all input registers are read. This is used to
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/// model the GCC inline asm '&' constraint modifier.
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bool IsEarlyClobber : 1;
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/// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
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/// not a real instruction. Such uses should be ignored during codegen.
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bool IsDebug : 1;
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/// SmallContents - This really should be part of the Contents union, but
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/// lives out here so we can get a better packed struct.
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/// MO_Register: Register number.
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/// OffsetedInfo: Low bits of offset.
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union {
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unsigned RegNo; // For MO_Register.
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unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
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} SmallContents;
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/// ParentMI - This is the instruction that this operand is embedded into.
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/// This is valid for all operand types, when the operand is in an instr.
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MachineInstr *ParentMI;
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/// Contents union - This contains the payload for the various operand types.
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union {
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
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const ConstantFP *CFP; // For MO_FPImmediate.
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const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
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int64_t ImmVal; // For MO_Immediate.
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const uint32_t *RegMask; // For MO_RegisterMask.
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const MDNode *MD; // For MO_Metadata.
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MCSymbol *Sym; // For MO_MCSymbol
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struct { // For MO_Register.
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// Register number is in SmallContents.RegNo.
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MachineOperand *Prev; // Access list for register. See MRI.
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MachineOperand *Next;
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} Reg;
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/// OffsetedInfo - This struct contains the offset and an object identifier.
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/// this represent the object as with an optional offset from it.
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struct {
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union {
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int Index; // For MO_*Index - The index itself.
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const char *SymbolName; // For MO_ExternalSymbol.
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const GlobalValue *GV; // For MO_GlobalAddress.
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const BlockAddress *BA; // For MO_BlockAddress.
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} Val;
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// Low bits of offset are in SmallContents.OffsetLo.
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int OffsetHi; // An offset from the object, high 32 bits.
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} OffsetedInfo;
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} Contents;
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explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
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TargetFlags = 0;
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}
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public:
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/// getType - Returns the MachineOperandType for this operand.
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///
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MachineOperandType getType() const { return (MachineOperandType)OpKind; }
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unsigned char getTargetFlags() const {
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return isReg() ? 0 : TargetFlags;
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}
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void setTargetFlags(unsigned char F) {
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assert(!isReg() && "Register operands can't have target flags");
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TargetFlags = F;
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}
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void addTargetFlag(unsigned char F) {
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assert(!isReg() && "Register operands can't have target flags");
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TargetFlags |= F;
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}
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/// getParent - Return the instruction that this operand belongs to.
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///
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MachineInstr *getParent() { return ParentMI; }
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const MachineInstr *getParent() const { return ParentMI; }
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/// clearParent - Reset the parent pointer.
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///
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/// The MachineOperand copy constructor also copies ParentMI, expecting the
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/// original to be deleted. If a MachineOperand is ever stored outside a
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/// MachineInstr, the parent pointer must be cleared.
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///
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/// Never call clearParent() on an operand in a MachineInstr.
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///
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void clearParent() { ParentMI = 0; }
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void print(raw_ostream &os, const TargetMachine *TM = 0) const;
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//===--------------------------------------------------------------------===//
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// Accessors that tell you what kind of MachineOperand you're looking at.
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//===--------------------------------------------------------------------===//
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/// isReg - Tests if this is a MO_Register operand.
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bool isReg() const { return OpKind == MO_Register; }
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/// isImm - Tests if this is a MO_Immediate operand.
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bool isImm() const { return OpKind == MO_Immediate; }
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/// isCImm - Test if t his is a MO_CImmediate operand.
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bool isCImm() const { return OpKind == MO_CImmediate; }
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/// isFPImm - Tests if this is a MO_FPImmediate operand.
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bool isFPImm() const { return OpKind == MO_FPImmediate; }
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/// isMBB - Tests if this is a MO_MachineBasicBlock operand.
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bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
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/// isFI - Tests if this is a MO_FrameIndex operand.
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bool isFI() const { return OpKind == MO_FrameIndex; }
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/// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
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bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
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/// isTargetIndex - Tests if this is a MO_TargetIndex operand.
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bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
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/// isJTI - Tests if this is a MO_JumpTableIndex operand.
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bool isJTI() const { return OpKind == MO_JumpTableIndex; }
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/// isGlobal - Tests if this is a MO_GlobalAddress operand.
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bool isGlobal() const { return OpKind == MO_GlobalAddress; }
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/// isSymbol - Tests if this is a MO_ExternalSymbol operand.
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bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
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/// isBlockAddress - Tests if this is a MO_BlockAddress operand.
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bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
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/// isRegMask - Tests if this is a MO_RegisterMask operand.
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bool isRegMask() const { return OpKind == MO_RegisterMask; }
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/// isMetadata - Tests if this is a MO_Metadata operand.
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bool isMetadata() const { return OpKind == MO_Metadata; }
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bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
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//===--------------------------------------------------------------------===//
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// Accessors for Register Operands
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//===--------------------------------------------------------------------===//
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/// getReg - Returns the register number.
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unsigned getReg() const {
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assert(isReg() && "This is not a register operand!");
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return SmallContents.RegNo;
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}
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unsigned getSubReg() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return (unsigned)SubReg;
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}
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bool isUse() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return !IsDef;
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}
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bool isDef() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsDef;
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}
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bool isImplicit() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsImp;
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}
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bool isDead() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsDead;
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}
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bool isKill() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsKill;
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}
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bool isUndef() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsUndef;
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}
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bool isInternalRead() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsInternalRead;
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}
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bool isEarlyClobber() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsEarlyClobber;
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}
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bool isTied() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return TiedTo;
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}
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bool isDebug() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return IsDebug;
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}
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/// readsReg - Returns true if this operand reads the previous value of its
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/// register. A use operand with the <undef> flag set doesn't read its
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/// register. A sub-register def implicitly reads the other parts of the
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/// register being redefined unless the <undef> flag is set.
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///
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/// This refers to reading the register value from before the current
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/// instruction or bundle. Internal bundle reads are not included.
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bool readsReg() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
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}
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//===--------------------------------------------------------------------===//
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// Mutators for Register Operands
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//===--------------------------------------------------------------------===//
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/// Change the register this operand corresponds to.
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///
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void setReg(unsigned Reg);
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void setSubReg(unsigned subReg) {
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assert(isReg() && "Wrong MachineOperand accessor");
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SubReg = (unsigned char)subReg;
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}
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/// substVirtReg - Substitute the current register with the virtual
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/// subregister Reg:SubReg. Take any existing SubReg index into account,
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/// using TargetRegisterInfo to compose the subreg indices if necessary.
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/// Reg must be a virtual register, SubIdx can be 0.
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///
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void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
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/// substPhysReg - Substitute the current register with the physical register
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/// Reg, taking any existing SubReg into account. For instance,
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/// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
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///
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void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
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void setIsUse(bool Val = true) { setIsDef(!Val); }
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void setIsDef(bool Val = true);
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void setImplicit(bool Val = true) {
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assert(isReg() && "Wrong MachineOperand accessor");
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IsImp = Val;
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}
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void setIsKill(bool Val = true) {
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assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
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assert((!Val || !isDebug()) && "Marking a debug operation as kill");
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IsKill = Val;
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}
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void setIsDead(bool Val = true) {
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assert(isReg() && IsDef && "Wrong MachineOperand accessor");
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IsDead = Val;
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}
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void setIsUndef(bool Val = true) {
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assert(isReg() && "Wrong MachineOperand accessor");
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IsUndef = Val;
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}
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void setIsInternalRead(bool Val = true) {
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assert(isReg() && "Wrong MachineOperand accessor");
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IsInternalRead = Val;
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}
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void setIsEarlyClobber(bool Val = true) {
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assert(isReg() && IsDef && "Wrong MachineOperand accessor");
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IsEarlyClobber = Val;
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}
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void setIsDebug(bool Val = true) {
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assert(isReg() && IsDef && "Wrong MachineOperand accessor");
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IsDebug = Val;
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}
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//===--------------------------------------------------------------------===//
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// Accessors for various operand types.
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//===--------------------------------------------------------------------===//
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int64_t getImm() const {
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assert(isImm() && "Wrong MachineOperand accessor");
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return Contents.ImmVal;
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}
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const ConstantInt *getCImm() const {
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assert(isCImm() && "Wrong MachineOperand accessor");
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return Contents.CI;
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}
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const ConstantFP *getFPImm() const {
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assert(isFPImm() && "Wrong MachineOperand accessor");
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return Contents.CFP;
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}
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MachineBasicBlock *getMBB() const {
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assert(isMBB() && "Wrong MachineOperand accessor");
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return Contents.MBB;
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}
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int getIndex() const {
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assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
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"Wrong MachineOperand accessor");
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return Contents.OffsetedInfo.Val.Index;
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}
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const GlobalValue *getGlobal() const {
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assert(isGlobal() && "Wrong MachineOperand accessor");
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return Contents.OffsetedInfo.Val.GV;
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}
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const BlockAddress *getBlockAddress() const {
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assert(isBlockAddress() && "Wrong MachineOperand accessor");
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return Contents.OffsetedInfo.Val.BA;
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}
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MCSymbol *getMCSymbol() const {
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assert(isMCSymbol() && "Wrong MachineOperand accessor");
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return Contents.Sym;
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}
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/// getOffset - Return the offset from the symbol in this operand. This always
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/// returns 0 for ExternalSymbol operands.
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int64_t getOffset() const {
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assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
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isBlockAddress()) && "Wrong MachineOperand accessor");
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return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
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SmallContents.OffsetLo;
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}
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const char *getSymbolName() const {
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assert(isSymbol() && "Wrong MachineOperand accessor");
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return Contents.OffsetedInfo.Val.SymbolName;
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}
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/// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
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/// It is sometimes necessary to detach the register mask pointer from its
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/// machine operand. This static method can be used for such detached bit
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/// mask pointers.
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static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
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// See TargetRegisterInfo.h.
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assert(PhysReg < (1u << 30) && "Not a physical register");
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return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
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}
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/// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
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bool clobbersPhysReg(unsigned PhysReg) const {
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return clobbersPhysReg(getRegMask(), PhysReg);
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}
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/// getRegMask - Returns a bit mask of registers preserved by this RegMask
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/// operand.
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const uint32_t *getRegMask() const {
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assert(isRegMask() && "Wrong MachineOperand accessor");
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return Contents.RegMask;
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}
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const MDNode *getMetadata() const {
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assert(isMetadata() && "Wrong MachineOperand accessor");
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return Contents.MD;
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}
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//===--------------------------------------------------------------------===//
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// Mutators for various operand types.
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//===--------------------------------------------------------------------===//
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void setImm(int64_t immVal) {
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assert(isImm() && "Wrong MachineOperand mutator");
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Contents.ImmVal = immVal;
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}
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void setOffset(int64_t Offset) {
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assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
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isBlockAddress()) && "Wrong MachineOperand accessor");
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SmallContents.OffsetLo = unsigned(Offset);
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Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
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}
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void setIndex(int Idx) {
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assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
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"Wrong MachineOperand accessor");
|
|
Contents.OffsetedInfo.Val.Index = Idx;
|
|
}
|
|
|
|
void setMBB(MachineBasicBlock *MBB) {
|
|
assert(isMBB() && "Wrong MachineOperand accessor");
|
|
Contents.MBB = MBB;
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Other methods.
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// isIdenticalTo - Return true if this operand is identical to the specified
|
|
/// operand. Note: This method ignores isKill and isDead properties.
|
|
bool isIdenticalTo(const MachineOperand &Other) const;
|
|
|
|
/// \brief MachineOperand hash_value overload.
|
|
///
|
|
/// Note that this includes the same information in the hash that
|
|
/// isIdenticalTo uses for comparison. It is thus suited for use in hash
|
|
/// tables which use that function for equality comparisons only.
|
|
friend hash_code hash_value(const MachineOperand &MO);
|
|
|
|
/// ChangeToImmediate - Replace this operand with a new immediate operand of
|
|
/// the specified value. If an operand is known to be an immediate already,
|
|
/// the setImm method should be used.
|
|
void ChangeToImmediate(int64_t ImmVal);
|
|
|
|
/// ChangeToRegister - Replace this operand with a new register operand of
|
|
/// the specified value. If an operand is known to be an register already,
|
|
/// the setReg method should be used.
|
|
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
|
|
bool isKill = false, bool isDead = false,
|
|
bool isUndef = false, bool isDebug = false);
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Construction methods.
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
static MachineOperand CreateImm(int64_t Val) {
|
|
MachineOperand Op(MachineOperand::MO_Immediate);
|
|
Op.setImm(Val);
|
|
return Op;
|
|
}
|
|
|
|
static MachineOperand CreateCImm(const ConstantInt *CI) {
|
|
MachineOperand Op(MachineOperand::MO_CImmediate);
|
|
Op.Contents.CI = CI;
|
|
return Op;
|
|
}
|
|
|
|
static MachineOperand CreateFPImm(const ConstantFP *CFP) {
|
|
MachineOperand Op(MachineOperand::MO_FPImmediate);
|
|
Op.Contents.CFP = CFP;
|
|
return Op;
|
|
}
|
|
|
|
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
|
|
bool isKill = false, bool isDead = false,
|
|
bool isUndef = false,
|
|
bool isEarlyClobber = false,
|
|
unsigned SubReg = 0,
|
|
bool isDebug = false,
|
|
bool isInternalRead = false) {
|
|
MachineOperand Op(MachineOperand::MO_Register);
|
|
Op.IsDef = isDef;
|
|
Op.IsImp = isImp;
|
|
Op.IsKill = isKill;
|
|
Op.IsDead = isDead;
|
|
Op.IsUndef = isUndef;
|
|
Op.IsInternalRead = isInternalRead;
|
|
Op.IsEarlyClobber = isEarlyClobber;
|
|
Op.TiedTo = 0;
|
|
Op.IsDebug = isDebug;
|
|
Op.SmallContents.RegNo = Reg;
|
|
Op.Contents.Reg.Prev = 0;
|
|
Op.Contents.Reg.Next = 0;
|
|
Op.SubReg = SubReg;
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateMBB(MachineBasicBlock *MBB,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
|
|
Op.setMBB(MBB);
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateFI(int Idx) {
|
|
MachineOperand Op(MachineOperand::MO_FrameIndex);
|
|
Op.setIndex(Idx);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateCPI(unsigned Idx, int Offset,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
|
|
Op.setIndex(Idx);
|
|
Op.setOffset(Offset);
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_TargetIndex);
|
|
Op.setIndex(Idx);
|
|
Op.setOffset(Offset);
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateJTI(unsigned Idx,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_JumpTableIndex);
|
|
Op.setIndex(Idx);
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_GlobalAddress);
|
|
Op.Contents.OffsetedInfo.Val.GV = GV;
|
|
Op.setOffset(Offset);
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateES(const char *SymName,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_ExternalSymbol);
|
|
Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
|
|
Op.setOffset(0); // Offset is always 0.
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
|
|
unsigned char TargetFlags = 0) {
|
|
MachineOperand Op(MachineOperand::MO_BlockAddress);
|
|
Op.Contents.OffsetedInfo.Val.BA = BA;
|
|
Op.setOffset(Offset);
|
|
Op.setTargetFlags(TargetFlags);
|
|
return Op;
|
|
}
|
|
/// CreateRegMask - Creates a register mask operand referencing Mask. The
|
|
/// operand does not take ownership of the memory referenced by Mask, it must
|
|
/// remain valid for the lifetime of the operand.
|
|
///
|
|
/// A RegMask operand represents a set of non-clobbered physical registers on
|
|
/// an instruction that clobbers many registers, typically a call. The bit
|
|
/// mask has a bit set for each physreg that is preserved by this
|
|
/// instruction, as described in the documentation for
|
|
/// TargetRegisterInfo::getCallPreservedMask().
|
|
///
|
|
/// Any physreg with a 0 bit in the mask is clobbered by the instruction.
|
|
///
|
|
static MachineOperand CreateRegMask(const uint32_t *Mask) {
|
|
assert(Mask && "Missing register mask");
|
|
MachineOperand Op(MachineOperand::MO_RegisterMask);
|
|
Op.Contents.RegMask = Mask;
|
|
return Op;
|
|
}
|
|
static MachineOperand CreateMetadata(const MDNode *Meta) {
|
|
MachineOperand Op(MachineOperand::MO_Metadata);
|
|
Op.Contents.MD = Meta;
|
|
return Op;
|
|
}
|
|
|
|
static MachineOperand CreateMCSymbol(MCSymbol *Sym) {
|
|
MachineOperand Op(MachineOperand::MO_MCSymbol);
|
|
Op.Contents.Sym = Sym;
|
|
return Op;
|
|
}
|
|
|
|
friend class MachineInstr;
|
|
friend class MachineRegisterInfo;
|
|
private:
|
|
//===--------------------------------------------------------------------===//
|
|
// Methods for handling register use/def lists.
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// isOnRegUseList - Return true if this operand is on a register use/def list
|
|
/// or false if not. This can only be called for register operands that are
|
|
/// part of a machine instruction.
|
|
bool isOnRegUseList() const {
|
|
assert(isReg() && "Can only add reg operand to use lists");
|
|
return Contents.Reg.Prev != 0;
|
|
}
|
|
};
|
|
|
|
inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
|
|
MO.print(OS, 0);
|
|
return OS;
|
|
}
|
|
|
|
// See friend declaration above. This additional declaration is required in
|
|
// order to compile LLVM with IBM xlC compiler.
|
|
hash_code hash_value(const MachineOperand &MO);
|
|
} // End llvm namespace
|
|
|
|
#endif
|