Chris Lattner 4172b10ca1 Use new PPC-specific nodes to represent shifts which require the 6-bit ... amount handling that PPC provides. These are generated by the lowering code and prevents the dag combiner from assuming (rightfully) that the shifts don't only look at 5 bits. This fixes a miscompilation of crafty with the new front-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-06 02:10:38 +00:00
..
Alpha	added instructions with inverted immediates	2005-12-06 00:33:53 +00:00
CBackend
IA64	Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.	2005-12-05 02:34:29 +00:00
PowerPC	Use new PPC-specific nodes to represent shifts which require the 6-bit	2005-12-06 02:10:38 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
Sparc	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV8	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	Remove unnecessary let hasCtrlDep=1 now it can be inferred.	2005-12-05 23:09:43 +00:00
Makefile
MRegisterInfo.cpp
SubtargetFeature.cpp
Target.td	* Added instruction property hasCtrlDep for those which r/w control-flow	2005-12-04 08:13:17 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSchedule.td
TargetSelectionDAG.td	On some targets (e.g. X86), shift amounts are not the same as the value	2005-12-05 02:37:26 +00:00
TargetSubtarget.cpp