Sanjay Patel b9736caa6a Fix a test that has no checks. ...

X86 doesn't have fneg, so check for xor.

Differential Revision: http://reviews.llvm.org/D4812


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214992 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-06 20:45:30 +00:00

..

AArch64

[AArch64] Add a testcase for r214957.

2014-08-06 13:31:32 +00:00

ARM

ARM: do not generate BLX instructions on Cortex-M CPUs.

2014-08-06 11:13:14 +00:00

CPP

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Generic

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

Hexagon

DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

2014-08-06 00:21:25 +00:00

Inputs

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Mips

llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit -mtriple=(mips|mipsel)-linux on 4 lines.

2014-08-01 22:15:38 +00:00

MSP430

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NVPTX

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PowerPC

[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian

2014-08-05 20:47:25 +00:00

R600

R600: Cleanup fadd and fsub tests

2014-08-06 20:27:55 +00:00

SPARC

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SystemZ

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Thumb

[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly

2014-08-02 05:40:40 +00:00

Thumb2

ARM: do not generate BLX instructions on Cortex-M CPUs.

2014-08-06 11:13:14 +00:00

X86

Fix a test that has no checks.

2014-08-06 20:45:30 +00:00

XCore

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