mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Apparently, the style needs to be agreed upon first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
358 lines
16 KiB
C++
358 lines
16 KiB
C++
//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// The Hexagon processor has no instructions that load or store predicate
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// registers directly. So, when these registers must be spilled a general
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// purpose register must be found and the value copied to/from it from/to
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// the predicate register. This code currently does not use the register
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// scavenger mechanism available in the allocator. There are two registers
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// reserved to allow spilling/restoring predicate registers. One is used to
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// hold the predicate value. The other is used when stack frame offsets are
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// too large.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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namespace llvm {
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FunctionPass *createHexagonExpandPredSpillCode();
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void initializeHexagonExpandPredSpillCodePass(PassRegistry&);
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}
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namespace {
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class HexagonExpandPredSpillCode : public MachineFunctionPass {
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public:
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static char ID;
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HexagonExpandPredSpillCode() : MachineFunctionPass(ID) {
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PassRegistry &Registry = *PassRegistry::getPassRegistry();
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initializeHexagonExpandPredSpillCodePass(Registry);
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}
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const char *getPassName() const override {
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return "Hexagon Expand Predicate Spill Code";
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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};
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char HexagonExpandPredSpillCode::ID = 0;
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bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
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const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
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const HexagonInstrInfo *TII = QST.getInstrInfo();
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock* MBB = MBBb;
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// Traverse the basic block.
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for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
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++MII) {
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MachineInstr *MI = MII;
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int Opc = MI->getOpcode();
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if (Opc == Hexagon::S2_storerb_pci_pseudo ||
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Opc == Hexagon::S2_storerh_pci_pseudo ||
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Opc == Hexagon::S2_storeri_pci_pseudo ||
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Opc == Hexagon::S2_storerd_pci_pseudo ||
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Opc == Hexagon::S2_storerf_pci_pseudo) {
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unsigned Opcode;
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if (Opc == Hexagon::S2_storerd_pci_pseudo)
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Opcode = Hexagon::S2_storerd_pci;
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else if (Opc == Hexagon::S2_storeri_pci_pseudo)
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Opcode = Hexagon::S2_storeri_pci;
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else if (Opc == Hexagon::S2_storerh_pci_pseudo)
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Opcode = Hexagon::S2_storerh_pci;
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else if (Opc == Hexagon::S2_storerf_pci_pseudo)
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Opcode = Hexagon::S2_storerf_pci;
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else if (Opc == Hexagon::S2_storerb_pci_pseudo)
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Opcode = Hexagon::S2_storerb_pci;
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else
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llvm_unreachable("wrong Opc");
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MachineOperand &Op0 = MI->getOperand(0);
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MachineOperand &Op1 = MI->getOperand(1);
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MachineOperand &Op2 = MI->getOperand(2);
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MachineOperand &Op3 = MI->getOperand(3); // Modifier value.
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MachineOperand &Op4 = MI->getOperand(4);
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// Emit a "C6 = Rn, C6 is the control register for M0".
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
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Hexagon::C6)->addOperand(Op3);
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// Replace the pseude circ_ldd by the real circ_ldd.
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MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Opcode));
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NewMI->addOperand(Op0);
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NewMI->addOperand(Op1);
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NewMI->addOperand(Op4);
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NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
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false, /*isDef*/
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false, /*isImpl*/
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true /*isKill*/));
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NewMI->addOperand(Op2);
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::L2_loadrd_pci_pseudo ||
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Opc == Hexagon::L2_loadri_pci_pseudo ||
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Opc == Hexagon::L2_loadrh_pci_pseudo ||
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Opc == Hexagon::L2_loadruh_pci_pseudo||
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Opc == Hexagon::L2_loadrb_pci_pseudo ||
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Opc == Hexagon::L2_loadrub_pci_pseudo) {
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unsigned Opcode;
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if (Opc == Hexagon::L2_loadrd_pci_pseudo)
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Opcode = Hexagon::L2_loadrd_pci;
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else if (Opc == Hexagon::L2_loadri_pci_pseudo)
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Opcode = Hexagon::L2_loadri_pci;
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else if (Opc == Hexagon::L2_loadrh_pci_pseudo)
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Opcode = Hexagon::L2_loadrh_pci;
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else if (Opc == Hexagon::L2_loadruh_pci_pseudo)
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Opcode = Hexagon::L2_loadruh_pci;
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else if (Opc == Hexagon::L2_loadrb_pci_pseudo)
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Opcode = Hexagon::L2_loadrb_pci;
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else if (Opc == Hexagon::L2_loadrub_pci_pseudo)
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Opcode = Hexagon::L2_loadrub_pci;
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else
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llvm_unreachable("wrong Opc");
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MachineOperand &Op0 = MI->getOperand(0);
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MachineOperand &Op1 = MI->getOperand(1);
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MachineOperand &Op2 = MI->getOperand(2);
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MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
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MachineOperand &Op5 = MI->getOperand(5);
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// Emit a "C6 = Rn, C6 is the control register for M0".
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
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Hexagon::C6)->addOperand(Op4);
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// Replace the pseude circ_ldd by the real circ_ldd.
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MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Opcode));
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NewMI->addOperand(Op1);
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NewMI->addOperand(Op0);
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NewMI->addOperand(Op2);
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NewMI->addOperand(Op5);
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NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
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false, /*isDef*/
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false, /*isImpl*/
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true /*isKill*/));
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::L2_loadrd_pbr_pseudo ||
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Opc == Hexagon::L2_loadri_pbr_pseudo ||
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Opc == Hexagon::L2_loadrh_pbr_pseudo ||
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Opc == Hexagon::L2_loadruh_pbr_pseudo||
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Opc == Hexagon::L2_loadrb_pbr_pseudo ||
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Opc == Hexagon::L2_loadrub_pbr_pseudo) {
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unsigned Opcode;
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if (Opc == Hexagon::L2_loadrd_pbr_pseudo)
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Opcode = Hexagon::L2_loadrd_pbr;
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else if (Opc == Hexagon::L2_loadri_pbr_pseudo)
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Opcode = Hexagon::L2_loadri_pbr;
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else if (Opc == Hexagon::L2_loadrh_pbr_pseudo)
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Opcode = Hexagon::L2_loadrh_pbr;
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else if (Opc == Hexagon::L2_loadruh_pbr_pseudo)
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Opcode = Hexagon::L2_loadruh_pbr;
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else if (Opc == Hexagon::L2_loadrb_pbr_pseudo)
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Opcode = Hexagon::L2_loadrb_pbr;
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else if (Opc == Hexagon::L2_loadrub_pbr_pseudo)
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Opcode = Hexagon::L2_loadrub_pbr;
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else
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llvm_unreachable("wrong Opc");
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MachineOperand &Op0 = MI->getOperand(0);
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MachineOperand &Op1 = MI->getOperand(1);
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MachineOperand &Op2 = MI->getOperand(2);
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MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
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// Emit a "C6 = Rn, C6 is the control register for M0".
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
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Hexagon::C6)->addOperand(Op4);
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// Replace the pseudo brev_ldd by the real brev_ldd.
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MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Opcode));
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NewMI->addOperand(Op1);
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NewMI->addOperand(Op0);
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NewMI->addOperand(Op2);
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NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
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false, /*isDef*/
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false, /*isImpl*/
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true /*isKill*/));
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::S2_storerd_pbr_pseudo ||
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Opc == Hexagon::S2_storeri_pbr_pseudo ||
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Opc == Hexagon::S2_storerh_pbr_pseudo ||
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Opc == Hexagon::S2_storerb_pbr_pseudo ||
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Opc == Hexagon::S2_storerf_pbr_pseudo) {
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unsigned Opcode;
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if (Opc == Hexagon::S2_storerd_pbr_pseudo)
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Opcode = Hexagon::S2_storerd_pbr;
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else if (Opc == Hexagon::S2_storeri_pbr_pseudo)
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Opcode = Hexagon::S2_storeri_pbr;
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else if (Opc == Hexagon::S2_storerh_pbr_pseudo)
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Opcode = Hexagon::S2_storerh_pbr;
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else if (Opc == Hexagon::S2_storerf_pbr_pseudo)
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Opcode = Hexagon::S2_storerf_pbr;
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else if (Opc == Hexagon::S2_storerb_pbr_pseudo)
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Opcode = Hexagon::S2_storerb_pbr;
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else
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llvm_unreachable("wrong Opc");
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MachineOperand &Op0 = MI->getOperand(0);
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MachineOperand &Op1 = MI->getOperand(1);
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MachineOperand &Op2 = MI->getOperand(2);
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MachineOperand &Op3 = MI->getOperand(3); // Modifier value.
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// Emit a "C6 = Rn, C6 is the control register for M0".
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
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Hexagon::C6)->addOperand(Op3);
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// Replace the pseudo brev_ldd by the real brev_ldd.
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MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Opcode));
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NewMI->addOperand(Op0);
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NewMI->addOperand(Op1);
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NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
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false, /*isDef*/
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false, /*isImpl*/
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true /*isKill*/));
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NewMI->addOperand(Op2);
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::STriw_pred) {
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// STriw_pred [R30], ofst, SrcReg;
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unsigned FP = MI->getOperand(0).getReg();
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assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
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"Not a Frame Pointer, Nor a Spill Slot");
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assert(MI->getOperand(1).isImm() && "Not an offset");
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int Offset = MI->getOperand(1).getImm();
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int SrcReg = MI->getOperand(2).getReg();
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assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
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"Not a predicate register");
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if (!TII->isValidOffset(Hexagon::S2_storeri_io, Offset)) {
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if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::CONST32_Int_Real),
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HEXAGON_RESERVED_REG_1).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
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HEXAGON_RESERVED_REG_1)
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.addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
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HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::S2_storeri_io))
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0).addReg(HEXAGON_RESERVED_REG_2);
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
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HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
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HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::S2_storeri_io))
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0)
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.addReg(HEXAGON_RESERVED_REG_2);
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}
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
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HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::S2_storeri_io)).
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addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
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}
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::LDriw_pred) {
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// DstReg = LDriw_pred [R30], ofst.
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int DstReg = MI->getOperand(0).getReg();
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assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
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"Not a predicate register");
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unsigned FP = MI->getOperand(1).getReg();
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assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
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"Not a Frame Pointer, Nor a Spill Slot");
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assert(MI->getOperand(2).isImm() && "Not an offset");
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int Offset = MI->getOperand(2).getImm();
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if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
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if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::CONST32_Int_Real),
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HEXAGON_RESERVED_REG_1).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
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HEXAGON_RESERVED_REG_1)
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.addReg(FP)
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.addReg(HEXAGON_RESERVED_REG_1);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
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HEXAGON_RESERVED_REG_2)
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
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DstReg).addReg(HEXAGON_RESERVED_REG_2);
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
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HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
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HEXAGON_RESERVED_REG_2)
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
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DstReg).addReg(HEXAGON_RESERVED_REG_2);
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}
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
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HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
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DstReg).addReg(HEXAGON_RESERVED_REG_2);
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}
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MII = MBB->erase(MI);
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--MII;
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}
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}
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}
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return true;
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}
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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static void initializePassOnce(PassRegistry &Registry) {
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const char *Name = "Hexagon Expand Predicate Spill Code";
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PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred",
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&HexagonExpandPredSpillCode::ID,
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nullptr, false, false);
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Registry.registerPass(*PI, true);
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}
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void llvm::initializeHexagonExpandPredSpillCodePass(PassRegistry &Registry) {
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CALL_ONCE_INITIALIZATION(initializePassOnce)
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}
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FunctionPass*
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llvm::createHexagonExpandPredSpillCode() {
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return new HexagonExpandPredSpillCode();
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}
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